SFR
Under
development
Preliminary Specifications REV.B3
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
41
Address
Register
018016
Group 3 waveform generate register 0
G3PO0
018116
018216
Group 3 waveform generate register 1
G3PO1
018316
018416
Group 3 waveform generate register 2
G3PO2
018516
018616
Group 3 waveform generate register 3
G3PO3
018716
018816
Group 3 waveform generate register 4
G3PO4
018916
018A16
Group 3 waveform generate register 5
G3PO5
018B16
018C16
Group 3 waveform generate register 6
G3PO6
018D16
018E16
Group 3 waveform generate register 7
G3PO7
018F16
019016 Group 3 waveform generate control register 0
G3POCR0
019116 Group 3 waveform generate control register 1
G3POCR1
019216 Group 3 waveform generate control register 2
G3POCR2
019316 Group 3 waveform generate control register 3
G3POCR3
019416 Group 3 waveform generate control register 4
G3POCR4
019516 Group 3 waveform generate control register 5
G3POCR5
019616 Group 3 waveform generate control register 6
G3POCR6
019716 Group 3 waveform generate control register 7
G3POCR7
019816
Group 3 waveform generate mask register 4
G3MK4
019916
019A16
Group 3 waveform generate mask register 5
G3MK5
019B16
019C16
Group 3 waveform generate mask register 6
G3MK6
019D16
019E16
Group 3 waveform generate mask register 7
G3MK7
019F16
01A016
Group 3 base timer register
G3BT
01A116
01A216 Group 3 base timer control register 0
G3BCR0
01A316 Group 3 base timer control register 1
G3BCR1
01A416
01A516
01A616 Group 3 function enable register
G3FE
01A716 Group 3 RTP output buffer register
G3RTP
01A816
01A916
01AA16
01AB16 Group 3 high-speed HDLC communication control register 1
HDLC1
01AC16 Group 3 high-speed HDLC communication control register
HDLC
01AD16 Group 3 high-speed HDLC communication register HDLCF
01AE16
Group 3 high-speed HDLC transmit counter
HDLCC
01AF16
Address
Register
01B016
Group 3 high-speed HDLC data compare register 0
HDLCCP0
01B116
01B216
Group 3 high-speed HDLC data mask register 0
HDLCMK0
01B316
01B416
Group 3 high-speed HDLC data compare register1
HDLCCP1
01B516
01B616
Group 3 high-speed HDLC data mask register 1
HDLCMK1
01B716
01B816
Group 3 high-speed HDLC data compare register 2
HDLCCP2
01B916
01BA16
Group 3 high-speed HDLC data mask register 2
HDLCMK2
01BB16
01BC16
Group 3 high-speed HDLC data compare register 3
HDLCCP3
01BD16
01BE16
Group 3 high-speed HDLC data mask register 3
HDLCMK3
01BF16
01C016
A-D1 register 0
AD10
01C116
01C216
A-D1 register 1
AD11
01C316
01C416
A-D1 register 2
AD12
01C516
01C616
A-D1 register 3
AD13
01C716
01C816
A-D1 register 4
AD14
01C916
01CA16
A-D1 register 5
AD15
01CB16
01CC16
A-D1 register 6
AD16
01CD16
01CE16
A-D1 register 7
AD17
01CF16
01D016
01D116
01D216
01D316
01D416 A-D1 control register 2
AD1CON2
01D516
01D616 A-D1 control register 0
AD1CON0
01D716 A-D1 control register 1
AD1CON1
01D816
01D916
01DA16
01DB16
01DC16
01DD16
01DE16
01DF16
The blank area is reserved and cannot be used by user.