CORRECT AND ERROR
M32C/83 GROUP DATA SHEET
Rev.
Date
Description
Page
Errror
Correct
( 7 / 7 )
344-
Electric characteristics
Add
380
385
Fig 1.34.1, Address 037716
Address 005716
_____
Bit 0: RY/BY status bit
_____
RY/BY signal status bit
385
Flash memory control register (address 005716)
_____
1st line: .....the RY/BY status flag.....
_____
.....the RY/BY signal status bit.....
390
13th line of Page Program Command (4116) and
_____
Fig 1.34.3: RY/BY status flag
_____
RY/BY signal status bit
391
11th line of Block Erase Command (2016/D016)
_____
and Fig 1.34.4: RY/BY status flag
_____
RY/BY signal status bit
392
_____
Fig 1.34.5: RY/BY status flag
_____
RY/BY signal status bit
400
3rd paragraph, 1st line
....., set the CLK1 pin to “H” level and....
....., set the CLK1 pin to “H” level and the TxD1 pin to
“L” level, and.....
400
3rd paragraph, 2nd line
The CLK1 pin is connected to Vcc.....resistance.
Add
401
P67 When using standard.....transfer.
Add
419
Fig 1.35.22, Data output
Pulled down
421
How frequency is identified, 2nd line: (2 - 20MHz) (2 - 30MHz)
2, 3
Table 1.1.1-2
Power consumption
26mA (f(XIN)=20MHz without software wait,Vcc=5V)
26mA (f(XIN)=20MHz without software wait,Vcc=3V)
37
SFR registers naming RAMD1, RAMD2, RAMD3
RMAD1, RMAD2, RMAD3
27, 37 001B16 VDC control register 1 VDC1
VDC control register 0
VDC0
001F16 VDC control register 0 VDC0
VDC control register 1
VDC1
39, 40 GiBF
GiRB
GiDR
GiTB
82
(4) VDC control register 0 (address 001F16)
VDC control register 0 (address 001B16)
VDC control register 1 (address 001F16)Add
92,
Figure 1.9.5, 1.12.1 RLVL register Note 3:
B3
28/3/
2002
273
Line 4
TxD output polarity reverse select bit is set to “0”
(not to reverse) for usual use.
TxD output polarity reverse select bit is set to “1” (re-
verse) for usual use.
328
Figure 1.29.18
IPS register when reset 0000 0X002 0016
412
Figure 1.35.12
RxD1 0F16
FF16
122
When this bit is 1, do not set the high-speed inter-
rupt select bit to 0.
When this bit is 1, set the high-speed interrupt select
bit to 0.
248
Figure 1.23.13. GiTMj register
When reset
000016
Indeterminate
247
Figure 1.23.11
GiTMCRj register CST0, CST1
CTS0, CTS1
252
Figure 1.23.16. GiPOj register, G3MKj register
When reset
XXXX16
Indeterminate
258
Figure 1.23.18. GiPOCR register
When reset
0X00 X0002
0016
270
Figure 1.23.26
GiBF register
GiRB register
269
Figure 1.23.30
GiDR register
GiTB register
B2
Feb/1/
2002
(continue
from
preced-
ing page)