Under
development
Preliminary Specifications REV.B3
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
Intelligent I/O
236
Ch0 TM/WG
register
16-bit
Base timer
PWM
output
Reset
Reset request from
communication block
Gr1 base timer reset
2 x (n+1)
Divider
f1
Edge
select
Digital
filter
Gate
function
Edge
select
Digital
filter
Gate
function
Edge
select
Digital
filter
Edge
select
Digital
filter
Edge
select
Digital
filter
Edge
select
Digital
filter
Edge
select
Digital
filter
Edge
select
Digital
filter
PWM
output
PWM
output
INPC00
INPC01
/ISCLK0
INPC02
/ISRxD0
INPC03
INPC04
INPC05
INPC06
INPC07
BTS
BT0S
DF
GT
PR
8
/
Ch0 to ch7
interrupt request signal
OUTC00/
IST x D0
OUTC01/
ISCLK0
OUTC04
OUTC05
Arbitration
Comparator
(8-bit)
Comparator
(8-bit)
Comparator
(8-bit)
Comparator
(8-bit)
Special
interrupt
check
4
/
Comparison
register
(8-bit)
Comparison
register
(8-bit)
Comparison
register
(8-bit)
Comparison
register
(8-bit)
4
/
Buffer
register
Data register
(8-bit)
Shift
register
4
/
Prescale
function
Prescale
function
Start bit
generation circuit
Bit insert circuit
SOF
generation circuit
Stop bit
generation circuit
Transmit latch
Transmit data
generation circuit
Transmit
CRC
Clock wait
control
circuit
SI/O transmit
buffer register
(8-bit)
Transmit
register
Transmit
buffer
Transmit output
register
(8-bit)
SI/O receive
buffer register
(8bit)
Receive data
generation circuit
Start bit
check
Bit insert
check
Stop bit
check
Receive
CRC
Receive input register
(8bit)
Polarity
reversing
Clock
selector
Clock
selector
TM input to Gr1
(When cascaded)
Start bit
HDLC data
process interrupt
Transmit interrupt
HDLC data
transmit interrupt
Receive interrupt
Special
communication
interrupt
WG input to Gr1
(When cascaded)
Polarity
reversing
Transmit
buffer
Receive
buffer
Receive shift
register
Receive shit
register
TM: Time Measurement
WG: Waveform Generation
Receive
buffer
Ch1 TM/WG
register
Ch2 TM register
Ch3 TM register
Ch4 TM/WG
register
Ch5 TM/WG
register
Ch6 TM register
Ch7 TM register
Transmission
Reception
Base timer carry output
(Note 1)
Transmit
shift register
Note 1: These pins aren’t connected with external pins in 100-pin version.
Note 2: Each register becomes reset status after supplying a clock by setting of the base timer control register 0.
Block diagrams for groups 0 to 3 are given in Figures 1.23.1 to 1.23.4.
Figure 1. 23. 1. Block diagram of intelligent I/O group 0