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Under
development
Preliminary Specifications REV.B3
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
Description
11
Figure 1.1.5. 100-pin version pin configuration (top view)
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
30
29
28
27
26
76
77
78
79
80
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
SS4
/
R
TS4
/
CTS4
/
TB4
IN
/
DA1
/
P9
4
SS3
/
R
TS3
/
CTS3
/
TB3
IN
/
DA0
/
P9
3
IE
OUT
/
OUTC2
0
/
SRxD3
/
SDA3
/
TxD3
/
TB2
IN
/
P9
2
IE
IN
/
STxD3
/
SCL3
/
RxD3
/
TB1
IN
/
P9
1
CLK3
/
TB0
IN
/
P9
0
BYTE
CNVss
V
CONT
/
X
CIN
/
P8
7
X
COUT
/
P8
6
RESET
X
OUT
Vss
X
IN
Vcc
NMI
/
P8
5
INT2
/
P8
4
CAN
IN
/
INT1
/
P8
3
CAN
OUT
/
OUTC3
2
/
INT0
/
P8
2
OUTC3
0
/
U
/
T
A
4
IN
/
P8
1
BE0
IN
/
ISRxD0
/INPC0
2
/
U
/
T
A
4
OUT
/
P8
0
CAN
IN
/
ISCLK0
/
OUTC0
1
/
INPC0
1
/
T
A
3
IN
/
P7
7
CAN
OUT
/
BE0
OUT
/
ISTxD0
/
OUTC0
0
/
INPC0
0
/
T
A
3
OUT
/
P7
6
BE1
IN
/ISRxD1
/
OUTC1
2
/
INPC1
2
/
W
/
T
A
2
IN
/
P7
5
ISCLK1
/
OUTC1
1
/
INPC1
1
/
W
/
T
A
2
OUT
/
P7
4
BE1
OUT
/
ISTxD1
/
OUTC1
0
/
SS2
/
R
TS2
/
CTS2
/
V
/
T
A
1
IN
/
P7
3
P42 / A18 ( MA10 )
P43 / A19 ( MA11 )
P44 / CS3 / A20 (MA12)
P45 / CS2 / A21
P46 / CS1 / A22
P47 / CS0 / A23
P50 / WRL / WR / CASL
P51 / WRH / BHE / CASH
P52 / RD / DW
P53 / CLKOUT / BCLK / ALE
P54 / HLDA / ALE
P55 / HOLD
P56 / ALE / RAS
P57 / RDY
P60 / CTS0 / RTS0 / SS0
P61 / CLK0
P62 / RxD0 / SCL0 / STxD0
P63 / TxD0 / SDA0 / SRxD0
P64 / CTS1 / RTS1 / SS1 / OUTC21 / ISCLK2
P65 / CLK1
P66 / RxD1 / SCL1 / STxD1
P67 / TxD1 / SDA1 / SRxD1
P70 / TA0OUT / TxD2 / SDA2 / SRxD2 / OUTC20
P71 / TA0IN / TB5IN / RxD2 / SCL2 / STxD2 / OUTC22
P72 / TA1OUT / V / CLK2
P1
3
/
D
11
P1
4
/
D
12
P1
5
/
D
13
/
INT3
P1
6
/
D
14
/
INT4
P1
7
/
D
15
/
INT5
P2
0
/
A
0
(
/
D
0
)
/
AN2
0
P2
1
/
A
1
(
/
D
1
)
/
AN2
1
P2
2
/
A
2
(
/
D
2
)
/
AN2
2
P2
3
/
A
3
(
/
D
3
)
/
AN2
3
P2
4
/
A
4
(
/
D
4
)
/
AN2
4
P2
5
/
A
5
(
/
D
5
)
/
AN2
5
P2
6
/
A
6
(
/
D
6
)
/
AN2
6
P2
7
/
A
7
(
/
D
7
)
/
AN2
7
Vss
P3
0
/
A
8
(
MA
0
)
(
/
D
8
)
Vcc
P3
1
/
A
9
(
MA
1
)
(
/
D
9
)
P3
2
/
A
10
(
MA
2
)
(
/
D
10
)
P3
3
/
A
11
(
MA
3
)
(
/
D
11
)
P3
4
/
A
12
(
MA
4
)
(
/
D
12
)
P3
5
/
A
13
(
MA
5
)
(
/
D
13
)
P3
6
/
A
14
(
MA
6
)
(
/
D
14
)
P3
7
/
A
15
(
MA
7
)
(
/
D
15
)
P4
0
/
A
16
(
MA
8
)
P4
1
/
A
17
(
MA
9
)
D10 / P12
D9 / P11
D8 / P10
D7 / AN07 / P07
D6 / AN06 / P06
D5 / AN05 / P05
D4 / AN04 / P04
D3 / AN03 / P03
D2 / AN02 / P02
D1 / AN01 / P01
D0 / AN00 / P00
KI3 / AN37 / P107
KI2 / AN36 / P106
KI1 / AN35 / P105
KI0 / AN34 / P104
AN33 / P103
AN32 / P102
AN31 / P101
AVss
AN30 / P100
VREF
AVcc
STxD4 / SCL4 / RxD4 / ADTRG / P97
SRxD4 / SDA4 / TxD4 / ANEX1 / P96
CLK4 / ANEX0 / P95
/ ISRxD2 / IEIN
/ ISTxD2 / IEOUT
M32C/83 (100P6Q-A)
Note: P70 and P71 are N-channel open drain output.