參數(shù)資料
型號(hào): ISP1761ET
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA128
封裝: 9 X 9 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT857-1, TFBGA-128
文件頁數(shù): 96/158頁
文件大?。?/td> 724K
代理商: ISP1761ET
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
96 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
[1]
The reserved bits should always be written with the reset value.
9.5.4
OTG Timer register
9.5.4.1
OTG Timer register (Low word S/C: 0388h/038Ah; high word S/C: 038Ch/038Eh)
This is a 32-bit register organized as two 16-bit fields. These two fields have separate set
and clear addresses.
Table 90
shows the bit allocation of the register.
Table 88:
Bit
Symbol
OTG Interrupt Enable Rise register: bit allocation
15
14
13
12
11
10
9
8
reserved
[1]
OTG_
SUSPEND
0
R
2
DP_SRP
OTG_TMR
_TIMEOUT
0
R/S/C
1
A_B_SESS
_VLD
0
R/S/C
B_SE0_
SRP
0
R/S/C
0
VBUS_VLD
Reset
Access
Bit
Symbol
0
0
0
0
0
R/S/C
7
B_SESS_
END
0
R/S/C
R/S/C
6
BDIS_
ACON
0
R/S/C
R/S/C
5
OTG_
RESUME
0
R/S/C
R/S/C
4
RMT_
CONN
0
R/S/C
R/S/C
3
ID
Reset
Access
0
0
0
R/S/C
R/S/C
R/S/C
Table 89:
Bit
15 to 11
10
9
8
OTG Interrupt Enable Rise register: bit description
Symbol
Description
-
reserved
OTG_SUSPEND
IRQ asserted when the bus is idle for more than 3 ms
OTG_TMR_TIMEOUT
IRQ asserted on OTG timer timeout
B_SE0_SRP
IRQ asserted when at least 2 ms of SE0 is detected in the
B-idle state
B_SESS_END
IRQ asserted when V
BUS
is less than 0.8 V
BDIS_ACON
IRQ asserted on BDIS_ACON condition
OTG_RESUME
IRQ asserted on J-K resume
RMT_CONN
IRQ asserted on RMT_CONN
ID
IRQ asserted on the ID pin transition from LOW to HIGH
DP_SRP
IRQ asserted when DP is asserted during SRP
A_B_SESS_VLD
IRQ asserted on the A-session valid for the A-device or on the
B-session valid for the B-device
VBUS_VLD
IRQ asserted on the rising edge of V
BUS
7
6
5
4
3
2
1
0
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