參數(shù)資料
型號(hào)： ISP1761ET
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Hi-Speed Universal Serial Bus On-The-Go controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA128
封裝： 9 X 9 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT857-1, TFBGA-128
文件頁數(shù)： 55/158頁
文件大?。?/td> 724K
代理商： ISP1761ET
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
55 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
Table 56:
Bit
31 to 11
10
HcInterruptEnable register: bit description
Symbol
Description
-
reserved; write logic 0
OTG_IRQ_E
OTG_IRQ Enable
: Controls the IRQ assertion because of events
present in the OTG Interrupt Latch register.
0 —
No IRQ will be asserted
1 —
IRQ will be asserted.
For details, see
Section 7.4
.
ISO_IRQ_E
ISO IRQ Enable
: Controls the IRQ assertion because of completing
one or more ISO PTDs matching the ISO IRQ Mask AND or
ISO IRQ Mask OR register bits combination.
0 —
No IRQ will be asserted because of completing ISO PTDs
1 —
IRQ will be asserted.
For details, see
Section 7.4
.
ATL_IRQ_E
ATL IRQ Enable
: Controls the IRQ assertion because of completing
one or more ATL PTDs matching the ATL IRQ Mask AND or
ATL IRQ Mask OR register bits combination.
0 —
No IRQ will be asserted because of completing ATL PTDs
1 —
IRQ will be asserted.
For details, see
Section 7.4
.
INT_IRQ_E
INT IRQ Enable
: Controls the IRQ assertion because of completing
one or more INT PTDs matching the INT IRQ Mask AND or
INT IRQ Mask OR register bits combination.
0 —
No IRQ will be asserted because of completing INT PTDs
1 —
IRQ will be asserted.
For details, see
Section 7.4
.
CLKREADY_E
Clock Ready Enable
: Enables the IRQ assertion when internal clock
signals are running stable. Useful after power-on or wake-up.
0 —
No IRQ will be generated after a CLKREADY_E event has
occurred
1 —
IRQ will be generated after a CLKREADY_E event.
HCSUSP_E
Host Controller Suspend Enable
: Enables the IRQ generation when
the Host Controller enters suspend mode.
0 —
No IRQ will be generated because of the Host Controller entering
suspend mode
1 —
IRQ will be generated at the Host Controller entering suspend
mode.
-
reserved; write logic 0
DMAEOT
INT_E
transfer completion.
0 —
No IRQ will be generated after the DMA transfer is completed
1 —
IRQ will be asserted because of the DMA transfer completion.
-
reserved; write logic 0
SOFITLINT_E
SOT ITL Interrupt Enable
: Controls the IRQ generation at every SOF
occurrence.
0 —
No IRQ will be generated on an SOF occurrence
1 —
IRQ will be asserted at every SOF.
9
8
7
6
5
4
3
DMA EOT Interrupt Enable
: Controls assertion of IRQ on the DMA
2 to 1
0
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ISP1761ET,551 功能描述:USB 接口集成電路 DO NOT USE ORDER -T OR NO "-" RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
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