參數(shù)資料
型號: ISP1761ET
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA128
封裝: 9 X 9 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT857-1, TFBGA-128
文件頁數(shù): 47/158頁
文件大?。?/td> 724K
代理商: ISP1761ET
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
47 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
[1]
The reserved bits should always be written with the reset value.
8.3.7
ATL Done Timeout register (R/W: 0338h)
The bit description of the ATL Done Timeout register is given in
Table 44
.
8.3.8
Memory register (R/W: 033Ch)
The Memory register contains the base memory read address and the respective bank.
This register needs to be set only before a first memory read cycle. Once written, the
address will be latched for the bank and will be incremented for every read of that bank
until a new address for that bank is written to change the address pointer.
The bit description of the register is given in
Table 45
.
Bit
Symbol
Reset
Access
Bit
Symbol
15
14
13
12
11
10
9
8
reserved
[1]
0
0
0
0
0
0
0
0
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
reserved
[1]
ISO_BUF_
FILL
0
R/W
INT_BUF_
FILL
0
R/W
ATL_BUF_
FILL
0
R/W
Reset
Access
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Table 43:
Bit
31 to 3
2
HcBufferStatus register: bit description
Symbol
Description
-
reserved
ISO_BUF_
FILL
1 —
Indicates one of the ISO PTDs is filled, and the ISO PTD area will
be processed
0 —
Indicates there is no PTD in this area. Therefore, processing of
the ISO PTDs will be completely skipped.
INT_BUF_
FILL
1 —
Indicates one of the INT PTDs is filled, and the INT PTD area will
be processed
0 —
Indicates there is no PTD in this area. Therefore, processing of
the INT PTDs will be completely skipped.
ATL_BUF_
FILL
1 —
Indicates one of the ATL PTDs is filled, and the ATL PTD area will
be processed
0 —
Indicates there is no PTD in this area. Therefore, processing of
the ATL PTDs will be completely skipped.
ISO Buffer Filled
:
1
INT Buffer Filled
:
0
ATL Buffer Filled
:
Table 44:
Bit
31 to 0 ATL_DONE_
TIMEOUT
[31:0]
ATL Done Timeout register: bit description
Symbol
Access
R/W
Value
0000 0000h
ATL Done Timeout
: This register determines the
ATL done timeout interrupt. This register defines
the timeout in ms after which the ISP1761 asserts
the INT line, if enabled. It is applicable to the ATL
done PTDs only.
Description
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