參數(shù)資料
型號： ISP1761ET
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Hi-Speed Universal Serial Bus On-The-Go controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA128
封裝： 9 X 9 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT857-1, TFBGA-128
文件頁數(shù)： 40/158頁
文件大?。?/td> 724K
代理商： ISP1761ET
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
40 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
[1]
For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal
Serial Bus Rev. 1.0
[2]
These fields read logic 0, if the PP (Port Power) bit in register PORTSC 1 is logic 0.
8.2.8
ISO PTD Done Map register (R: 0130h)
The bit description of the register is given in
Table 25
.
This register represents a direct map of the done status of the 32 PTDs. The bit
corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is
completed. Reading the Done Map register will clear all the bits that are set to logic 1, and
the next reading will reflect the updated status of new executed PTDs.
8.2.9
ISO PTD Skip Map register (R/W: 0134h)
Table 26
shows the bit description of the register.
When a bit in the PTD Skip Map is set to logic 1 that PTD will be skipped although its V bit
may be set. The information in that PTD is not processed. For example, NextPTDPointer
will not affect the order of processing of PTDs. The Skip bit should not be normally set on
the position indicated by NextPTDPointer.
8.2.10
ISO PTD Last PTD register (R/W: 0138h)
Table 27
shows the bit description of the ISO PTD Last PTD register.
2
PED
Port Enabled/Disabled
: Logic 1 means enable. Logic 0 means
disable.
[2]
Connect Status Change
: Logic 1 means change in ECCS. Logic 0
means no change.
[2]
Current Connect Status
: Logic 1 indicates a peripheral is present on
the port. Logic 0 indicates no peripheral is present.
[2]
1
ECSC
0
ECCS
Table 24:
Bit
PORTSC 1 register: bit description
…continued
Symbol
Description
[1]
Table 25:
Bit
31 to 0
ISO PTD Done Map register: bit description
Symbol
Access Value
ISO_PTD_DONE
_MAP[31:0]
Description
ISO PTD Done Map
: Done map for each of
the 32 PTDs for the ISO transfer
R
0000 0000h
Table 26:
Bit
31 to 0
ISO PTD Skip Map register: bit description
Symbol
Access
ISO_PTD_SKIP_
MAP[31:0]
Value
FFFF FFFFh
Description
ISO PTD Skip Map
: Skip map for each
of the 32 PTDs for the ISO transfer
R/W
Table 27:
Bit
31 to 0
ISO PTD Last PTD register: bit description
Symbol
Access
ISO_PTD_
LAST_
PTD[31:0]
Value
0000 0000h
Description
ISO PTD last PTD
: Last PTD of the 32 PTDs.
1h —
One PTD in ISO
2h —
Two PTDs in ISO
4h —
Three PTDs in ISO.
R/W
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參數(shù)描述
ISP1761ET,518 功能描述:USB 接口集成電路 USB 2.0 HS OTG HOST RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1761ET,551 功能描述:USB 接口集成電路 DO NOT USE ORDER -T OR NO "-" RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1761ET,557 功能描述:USB 接口集成電路 USB 2.0 HS OTG HOST RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1761ETGE 功能描述:IC USB CTRL HI-SPEED 128TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
ISP1761ET-S 功能描述:IC USB OTG CONTROLLER 128TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
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