參數(shù)資料
型號: ISP1761ET
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA128
封裝: 9 X 9 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT857-1, TFBGA-128
文件頁數(shù): 125/158頁
文件大?。?/td> 724K
代理商: ISP1761ET
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
125 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
When the PWRON bit in the Mode register is logic 1, the chip is powered. In such a case,
you do not need to issue the Unlock command because the microprocessor is powered
and therefore, the RD_N, WR_N and CS_N signals maintain their states.
When the PWRON bit is logic 0, the RD_N, WR_N and CS_N signals are floating because
the microprocessor is not powered. To protect the ISP1761 registers from being corrupted
during suspend, register write is locked when the chip goes into suspend. Therefore, you
need to issue the Unlock command to unlock the ISP1761 registers.
10.7.6
Interrupt Pulse Width register (R/W: 0280h)
Table 146
shows the bit description of the register.
10.7.7
Test Mode register (R/W: 0284h)
This 1 B register allows the firmware to set the DP and DM pins to predetermined states
for testing purposes. The bit allocation is given in
Table 147
.
Remark:
Only one bit can be set to logic 1 at a time.
[1]
The reserved bits should always be written with the reset value.
Table 145: Unlock Device register: bit description
Bit
Symbol
15 to 0
ULCODE[15:0]
Description
Unlock Code
: Writing data AA37h unlocks the internal registers
and FIFOs for writing, following a resume.
Table 146: Interrupt Pulse Width register: bit description
Bit
Symbol
Access Value
15 to 0 INTR_PULSE
_WIDTH[15:0
Description
Interrupt Pulse Width
: The interrupt signal pulse
width is configurable while it is in the pulse signaling
mode. The minimum pulse width is 3.33 ns when this
register is set to logic 1. The power-on reset value of
1Eh allows a pulse of 1
μ
s to be generated.
R/W
001Eh
Table 147: Test Mode register: bit allocation
Bit
7
Symbol
FORCEHS
Reset
0
Bus reset
0
Access
R/W
6
5
4
3
2
1
0
reserved
[1]
FORCEFS
0
0
R/W
PRBS
0
0
R/W
KSTATE
0
0
R/W
JSTATE
0
0
R/W
SE0_NAK
0
0
R/W
0
0
0
0
R/W
R/W
Table 148: Test Mode register: bit description
Bit
Symbol
7
FORCEHS
Description
Force High-Speed
: Logic 1
[1]
forces the hardware to the high-speed
mode only and disables the chirp detection logic.
reserved.
Force Full-Speed
: Logic 1
[1]
forces the physical layer to the full-speed
mode only and disables the chirp detection logic.
Logic 1
[2]
sets the DP and DM pins to toggle in a predetermined
random pattern.
6 to 5
4
-
FORCEFS
3
PRBS
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