參數(shù)資料
型號: ISP1761ET
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA128
封裝: 9 X 9 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT857-1, TFBGA-128
文件頁數(shù): 123/158頁
文件大小: 724K
代理商: ISP1761ET
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
123 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
10.7.2
DcChipID register (R: 0270h)
This read-only register contains the chip identification and the hardware version numbers.
The firmware should check this information to determine the functions and features
supported. The register contains 3 B, and the bit allocation is shown in
Table 139
.
10.7.3
Frame Number register (R: 0274h)
This read-only register contains the frame number of the last successfully received
Start-Of-Frame (SOF). The register contains 2 B, and the bit allocation is given in
Table 140
. In the case of 8-bit access, the register content is returned lower byte first.
2
PSOF
Pseudo SOF interrupt:
Logic 1 indicates that a pseudo SOF or
μ
SOF
was received. Pseudo SOF is an internally generated clock signal
(full-speed: 1 ms period, high-speed: 125
μ
s period) synchronized to
the USB bus SOF or
μ
SOF.
SOF interrupt:
Logic 1 indicates that a SOF or
μ
SOF was received.
Bus Reset
: Logic 1 indicates that a USB bus reset was detected.
When the SW_SEL_HC_DC bit in the OTG Control register is set,
BRESET will not be set, instead, this interrupt bit will report SE0 on DP
and DM for 2 ms.
1
0
SOF
BRESET
Table 138: DcInterrupt register: bit description
…continued
Bit
Symbol
Description
Table 139: DcChipID register: bit description
Bit
Symbol
Access
31 to 0
CHIPID
[31:0]
Value
0015 8210h
Description
Chip ID
: This registers represents the hardware
version number (0015h) and the chip ID (8210h) for
the Peripheral Controller.
R
Table 140: Frame Number register: bit allocation
Bit
15
Symbol
reserved
Power Reset
0
Bus Reset
0
Access
R
Bit
7
Symbol
Power Reset
0
Bus Reset
0
Access
R
14
13
12
11
10
9
8
MICROSOF[2:0]
0
0
R
4
SOFR[10:8]
0
0
R
1
0
0
R
6
0
0
R
5
0
0
R
3
0
0
R
2
0
0
R
0
SOFR[7:0]
0
0
R
0
0
R
0
0
R
0
0
R
0
0
R
0
0
R
0
0
R
Table 141: Frame Number register: bit description
Bit
Symbol
15 to 14
-
13 to 11
MICROSOF[2:0]
10 to 0
SOFR[10:0]
Description
reserved
microframe number
frame number
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