參數(shù)資料
型號(hào): ISP1761ET
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA128
封裝: 9 X 9 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT857-1, TFBGA-128
文件頁數(shù): 53/158頁
文件大?。?/td> 724K
代理商: ISP1761ET
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
53 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
[1]
The reserved bits should always be written with the reset value.
Bit
Symbol
7
6
5
4
3
2
1
0
INT_IRQ
CLK
READY
0
R/W
HCSUSP
reserved
[1]
DMA
EOTINT
0
R/W
reserved
[1]
SOFITLINT
Reset
Access
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Table 54:
Bit
31 to 11
10
HcInterrupt register: bit description
Symbol
Description
-
reserved; write logic 0
OTG_IRQ
OTG_IRQ
: Indicates that IRQ was asserted because of events present in
the OTG Interrupt Latch register.
0 —
No IRQ was asserted
1 —
IRQ was asserted.
For details, see
Section 7.4
.
ISO_IRQ
ISO IRQ
: Indicates that IRQ was asserted because an ISO PTD was
completed, or the PTDs corresponding to the bits set in the ISO IRQ
Mask AND or ISO IRQ Mask OR register bits combination were
completed.
0 —
No IRQ assertion determined by the completion of ISO PTDs
1 —
IRQ asserted because of completing ISO PTDs.
For details, see
Section 7.4
.
ATL_IRQ
ATL IRQ
: Indicates that an IRQ was asserted because an ATL PTD was
completed, or the PTDs corresponding to the bits set in the ATL IRQ
Mask AND or ATL IRQ Mask OR register bits combination were
completed.
0 —
No IRQ assertion determined by the completion of ATL PTDs
1 —
IRQ asserted because of completing ATL PTD.
For details, see
Section 7.4
.
INT_IRQ
INT IRQ
: Indicates that an IRQ was asserted because an INT PTD was
completed, or the PTDs corresponding to the bits set in the INT IRQ
Mask AND or INT IRQ Mask OR register bits combination were
completed.
0 —
No IRQ assertion determined by the completion of INT PTDs
1 —
IRQ asserted because of completing INT PTD.
For details, see
Section 7.4
.
CLKREADY
Clock Ready
: Indicates that IRQ was asserted as the internal clock
signals are running stable. Useful after a power-on or wake-up cycle.
0 —
No CLKREADY event has occurred
1 —
IRQ generated because of a CLKREADY event.
9
8
7
6
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