參數資料
型號： ISP1761ET
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Hi-Speed Universal Serial Bus On-The-Go controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA128
封裝： 9 X 9 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT857-1, TFBGA-128
文件頁數： 152/158頁
文件大小： 724K
代理商： ISP1761ET
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
152 of 158
continued >>
26. Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Ordering information . . . . . . . . . . . . . . . . . . . . .4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .7
Port connection scenarios . . . . . . . . . . . . . . . .16
Memory address . . . . . . . . . . . . . . . . . . . . . . .18
Using the IRQ Mask AND or IRQ Mask OR
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Hybrid mode . . . . . . . . . . . . . . . . . . . . . . . . . .28
Pin status during hybrid mode . . . . . . . . . . . . .28
Host Controller-specific register overview . . . .31
CAPLENGTH register: bit description . . . . . . .32
Table 10: HCIVERSION register: bit description . . . . . . .32
Table 11: HCSPARAMS register: bit allocation . . . . . . . .33
Table 12: HCSPARAMS register: bit description . . . . . . .33
Table 13: HCCPARAMS register: bit allocation . . . . . . . .34
Table 14: HCCPARAMS register: bit description . . . . . . .34
Table 15: USBCMD register: bit allocation . . . . . . . . . . .35
Table 16: USBCMD register: bit description . . . . . . . . . .35
Table 17: USBSTS register: bit allocation . . . . . . . . . . . .36
Table 18: USBSTS register: bit description . . . . . . . . . . .36
Table 19: FRINDEX register: bit allocation . . . . . . . . . . .37
Table 20: FRINDEX register: bit description . . . . . . . . . .37
Table 21: CONFIGFLAG register: bit allocation . . . . . . .38
Table 22: CONFIGFLAG register: bit description . . . . . .38
Table 23: PORTSC 1 register: bit allocation . . . . . . . . . .39
Table 24: PORTSC 1 register: bit description . . . . . . . . .39
Table 25: ISO PTD Done Map register: bit description . .40
Table 26: ISO PTD Skip Map register: bit description . . .40
Table 27: ISO PTD Last PTD register: bit description . . .40
Table 28: INT PTD Done Map register: bit description . .41
Table 29: INT PTD Skip Map register: bit description . . .41
Table 30: INT PTD Last PTD register: bit description . . .41
Table 31: ATL PTD Done Map register: bit description . .42
Table 32: ATL PTD Skip Map register: bit description . . .42
Table 33: ATL PTD Last PTD register: bit description . . .42
Table 34: HW Mode Control register: bit allocation . . . . .43
Table 35: HW Mode Control register: bit description . . . .43
Table 36: HcChipID register: bit description . . . . . . . . . .44
Table 37: HcScratch register: bit description . . . . . . . . . .44
Table 38: SW Reset register: bit allocation . . . . . . . . . . .45
Table 39: SW Reset register: bit description . . . . . . . . . .45
Table 40: HcDMAConfiguration register: bit allocation . .45
Table 41: HcDMAConfiguration register: bit description .46
Table 42: HcBufferStatus register: bit allocation . . . . . . .46
Table 43: HcBufferStatus register: bit description . . . . . .47
Table 44: ATL Done Timeout register: bit description . . .47
Table 45: Memory register: bit allocation . . . . . . . . . . . . .48
Table 46: Memory register: bit description . . . . . . . . . . .48
Table 47: Edge Interrupt Count register: bit allocation . .48
Table 6:
Table 7:
Table 8:
Table 9:
Table 48: Edge Interrupt Count register: bit description .49
Table 49: DMA Start Address register: bit allocation . . .49
Table 50: DMA Start Address register: bit description . .50
Table 51: Power Down Control register: bit allocation . .50
Table 52: Power Down Control register: bit description .51
Table 53: HcInterrupt register: bit allocation . . . . . . . . . .52
Table 54: HcInterrupt register: bit description . . . . . . . . .53
Table 55: HcInterruptEnable register: bit allocation . . . .54
Table 56: HcInterruptEnable register: bit description . . .55
Table 57: ISO IRQ MASK OR register: bit description . .56
Table 58: INT IRQ MASK OR register: bit description . .56
Table 59: ATL IRQ MASK OR register: bit description . .56
Table 60: ISO IRQ MASK AND register: bit description .57
Table 61: INT IRQ MASK AND register: bit description .57
Table 62: ATL IRQ MASK SAND register: bit description 57
Table 63: High-speed bulk IN and OUT, QHA: bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table 64: High-speed bulk IN and OUT, QHA: bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 65: High-speed isochronous IN and OUT, iTD: bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Table 66: High-speed isochronous IN and OUT, iTD: bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 67: High-speed interrupt IN and OUT, QHP: bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Table 68: High-speed interrupt IN and OUT, QHP: bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Table 69: Start and complete split for bulk, QHASS/CS: bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Table 70: Start and complete split for bulk, QHASS/CS: bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 71: Start and complete split for isochronous, SiTD: bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Table 72: Start and complete split for isochronous, SiTD: bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Table 73: Start and complete split for interrupt: bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Table 74: Start and complete split for interrupt: bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Table 75: OTG Controller-specific register overview . . . .90
Table 76: Address mapping of registers: 32-bit data bus
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Table 77: Address mapping of registers: 16-bit data bus
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Table 78: Vendor ID register: bit description . . . . . . . . . .91
Table 79: Product ID register: bit description . . . . . . . . .91
Table 80: OTG Control register: bit allocation . . . . . . . . .92
Table 81: OTG Control register: bit description . . . . . . . .92
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相關代理商/技術參數
參數描述
ISP1761ET,518 功能描述:USB 接口集成電路 USB 2.0 HS OTG HOST RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1761ET,551 功能描述:USB 接口集成電路 DO NOT USE ORDER -T OR NO "-" RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1761ET,557 功能描述:USB 接口集成電路 USB 2.0 HS OTG HOST RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1761ETGE 功能描述:IC USB CTRL HI-SPEED 128TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
ISP1761ET-S 功能描述:IC USB OTG CONTROLLER 128TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
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