參數(shù)資料
型號: ISP1761ET
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA128
封裝: 9 X 9 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT857-1, TFBGA-128
文件頁數(shù): 132/158頁
文件大?。?/td> 724K
代理商: ISP1761ET
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
132 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
15. Dynamic characteristics
[1]
Recommended accuracy of the clock frequency is 50 ppm for the crystal and oscillator. The oscillator used depends on V
CC(I/O)
.
Recommended values for external capacitors when using a crystal are 22 pF to 27 pF.
[2]
Table 157: Dynamic characteristics: system clock timing
Symbol
Parameter
Crystal oscillator
f
clk
clock frequency
[1]
Conditions
Min
Typ
Max
Unit
crystal
[2]
oscillator
-
-
12
12
-
-
MHz
MHz
External clock input
J
δ
V
clk
t
CR
, t
CF
external clock jitter
clock duty cycle
amplitude
rise time and fall time
-
-
-
-
-
50
V
CC(I/O)
-
500
-
-
3
ps
%
V
ns
Table 158: Dynamic characteristics: CPU interface block
V
CC(I/O)
= 1.65 V to 3.6 V; T
amb
=
40
°
C to +85
°
C; unless otherwise specified.
Symbol
Parameter
SR
output slew rate (rise, fall)
Conditions
standard load
Min
1
Typ
-
Max
4
Unit
V/ns
Table 159: Dynamic characteristics: high-speed source electrical characteristics
V
CC(I/O)
= 1.65 V to 3.6 V; T
amb
=
40
°
C to +85
°
C; unless otherwise specified.
Symbol
Parameter
Driver characteristics
t
HSR
high-speed differential rise
time
t
HSF
high-speed differential fall time 90 % to 10 %
Z
HSDRV
drive output resistance (this
also serves as a high-speed
termination)
Clock timing
t
HSDRAT
data rate
t
HSFRAM
microframe interval
t
HSRFI
consecutive microframe
interval difference
Conditions
Min
Typ
Max
Unit
10 % to 90 %
500
-
-
ps
500
40.5
-
45
-
49.5
ps
includes the R
S
resistor
479.76
124.9375
1
-
-
-
480.24
125.0625
four
high-speed
bit times
Mbit/s
μ
s
ns
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