參數(shù)資料
型號: ISP1761ET
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA128
封裝: 9 X 9 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT857-1, TFBGA-128
文件頁數(shù): 30/158頁
文件大?。?/td> 724K
代理商: ISP1761ET
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
30 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
7.9 Power-On Reset (POR)
When V
CC(5V0)
is directly connected to the RESET_N pin, the internal POR pulse width
(t
PORP
) will be typically 800 ns. The pulse is started when V
CC(5V0)
rises above V
TRIP
(1.2 V).
To give a better view of the functionality,
Figure 11
shows a possible curve of V
CC(5V0)
with
dips at t2–t3 and t4–t5. If the dip at t4–t5 is too short (that is, < 11
μ
s), the internal POR
pulse will not react and will remain LOW. The internal POR starts with a 1 at t0. At t1, the
detector will see the passing of the trip level and a delay element will add another t
PORP
before it drops to 0.
The internal POR pulse will be generated whenever V
CC(5V0)
drops below V
TRIP
for more
than 11
μ
s.
The recommended RESET input pulse length at power-on should be at least 2 ms to
ensure that internal clocks are stable.
The RESET_N pin can be either connected to V
CC(I/O)
(using the internal POR circuit) or
externally controlled (by the microcontroller, ASIC, and so on).
Figure 12
shows the
availability of the clock with respect to the external POR.
(1) PORP = Power-On Reset Pulse.
Fig 11. Internal power-on reset timing
Stable external clock is available at A.
Fig 12. Clock with respect to the external power-on reset
004aaa584
V
CC(5V0)
t0
t1
t2
t3
t4
t5
V
TRIP
t
PORP
PORP
(1)
t
PORP
RESET_N
EXTERNAL CLOCK
A
004aaa583
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