參數(shù)資料
型號： ISP1761ET
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Hi-Speed Universal Serial Bus On-The-Go controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA128
封裝： 9 X 9 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT857-1, TFBGA-128
文件頁數(shù)： 85/158頁
文件大小： 724K
代理商： ISP1761ET
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
85 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
peripheral, and the A-device assumes the role of a host. The A-device detects that the
B-device can support HNP by getting the OTG descriptor from the B-device. The A-device
will then enable the HNP hand-off by using SetFeature (b_hnp_enable) and then go into
the suspend state. The B-device signals claiming the host role by deasserting its pull-up
resistor. The A-device acknowledges by going into the peripheral state. The B-device then
assumes the role of a host and communicates with the A-device as long as it wishes.
When the B-device finishes communicating with the A-device, both the devices finally go
into the idle state. See
Figure 15
and
Figure 16
.
9.3 Session Request Protocol (SRP)
As a dual-role device, the ISP1761 can initiate and respond to SRP. The B-device initiates
SRP by data line pulsing, followed by V
BUS
pulsing. The A-device can detect either data
line pulsing or V
BUS
pulsing.
9.3.1
B-device initiating SRP
The ISP1761 can initiate SRP by performing the following steps:
1. Detect initial conditions [read B_SESS_END and B_SE0_SRP (bits 7 and 8) of the
OTG Status register].
2. Start data line pulsing [set DP_PULLUP (bit 0) of the OTG Control (set) register to
logic 1].
3. Wait for 5 ms to 10 ms.
4. Stop data line pulsing [set DP_PULLUP (bit 0) of the OTG Control (clear) register to
logic 0].
5. Start V
BUS
pulsing [set VBUS_CHRG (bit 6) of the OTG Control (set) register to
logic 1].
6. Wait for 10 ms to 20 ms.
7. Stop V
BUS
pulsing [set VBUS_CHRG (bit 6) of the OTG Control (clear) register to
logic 0].
8. Discharge V
BUS
for about 30 ms [by using VBUS_DISCHRG (bit 5) of the OTG
Control (set) register], optional.
The B-device must complete both data line pulsing and V
BUS
pulsing within 100 ms.
9.3.2
A-device responding to SRP
The A-device must be able to respond to one of the two SRP events: data line pulsing or
V
BUS
pulsing. When data line pulsing is used, the ISP1761 can detect DP pulsing. This
means that the peripheral-only device must initiate data line pulsing through DP. A
dual-role device will always initiate data line pulsing through DP.
To enable the SRP detection through the V
BUS
pulsing, set A_B_SESS_VLD (bit 1) in the
OTG Interrupt Enable Fall and OTG Interrupt Enable Rise registers.
To enable the SRP detection through the DP pulsing, set DP_SRP (bit 2) in the OTG
Interrupt Enable Rise register.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1761ET,518 功能描述:USB 接口集成電路 USB 2.0 HS OTG HOST RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1761ET,551 功能描述:USB 接口集成電路 DO NOT USE ORDER -T OR NO "-" RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1761ET,557 功能描述:USB 接口集成電路 USB 2.0 HS OTG HOST RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1761ETGE 功能描述:IC USB CTRL HI-SPEED 128TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
ISP1761ET-S 功能描述:IC USB OTG CONTROLLER 128TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
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