參數(shù)資料
型號(hào): Intel387 sx
廠商: Intel Corp.
英文描述: SX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器)
中文描述: 山西數(shù)學(xué)協(xié)處理器(32位數(shù)學(xué)協(xié)處理器)
文件頁數(shù): 46/47頁
文件大?。?/td> 443K
代理商: INTEL387 SX
Intel387
TM
SX MATH COPROCESSOR
A.1.2 EXCEPTIONS
A number of differences exist due to changes in the IEEE standard and to functional improvements to the
architecture of the Intel387 SX Math CoProcessor:
1. When the overflow or underflow exception is masked, the Intel387 SX Math CoProcessor differs from the
80287 in rounding when overflow or underflow occurs. The Intel387 SX Math CoProcessor produces
results that are consistent with the rounding mode.
2. When the underflow exception is masked, the Intel387 SX Math CoProcessor sets its underflow flag only if
there is also a loss of accuracy during denormalization.
3. Fewer invalid-operations exceptions due to denormal operand, because the instructions FSQRT, FDIV,
FPREM, and conversions to BCD or to integer normalize denormal operands before proceeding.
4. The FSQRT, FBSTP, and FPREM instructions may cause underflow, because they support denormal
operands.
5. The denormal exception can occur during the transcendental instruction and the FXTRACT instruction.
6. The denormal exception no longer takes precedence over all other exceptions.
7. When the denormal exception is masked, the Intel387 SX Math CoProcessor automatically normalizes
denormal operands. The 8087/80287 performs unnormal arithmetic, which might produce an unnormal
result.
8. When the operand is zero, the FXTRACT instruction reports a zero-divide exception and leaves
b
%
in
ST(1).
9. The status word has a new bit (SF) that signals when invalid-operation exceptions are due to stack
underflow or overflow.
10. FLD extended precision no longer reports denormal exceptions, because the instruction is not numeric.
11. FLD single/double precision when the operand is denormal converts the number to extended precision
and signals the denormal operand exception. When loading a signaling NaN, FLDsingle/double precision
signals an invalid-operation exception.
12. The Intel387 SX Math CoProcessor only generates quiet NaNs (as on the 80287); however, the Intel387
SX Math CoProcessor distinguishes between quiet NaNs and signaling NaNs. Signaling NaNs trigger
exceptions when they are used as operands; quiet NaNs do not (except for FCOM, FIST, and FBSTP
which also raise IE for quiet NaNs).
13. When stack overflow occurs during FPTAN and overflow is masked, both ST(0) and ST(1) contain quiet
NaNs. The 80287/8087 leaves the original operand in ST(1) intact.
14. When the scaling factor is
g
%
, the FSCALE instruction behaves as follows:
#
FSCALE (0,
%
) generates the invalid operation exception.
#
FSCALE (finite,
b
%
) generates zero with the same sign as the scaled operand.
#
FSCALE (finite,
a
%
) generates
%
with the same sign as the scaled operand.
The 8087/80287 returns zero in the first case and raises the invalid-operation exception in the other
cases.
15. The Intel387 SX Math CoProcessor returns signed infinity/zero as the unmasked response to massive
overflow/underflow. The 8087 and 80287 support a limited range for the scaling factor; within this range
either massive overflow/underflow do not occur or undefined results are produced.
A-2
46
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