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參數(shù)資料
| 型號： | Intel387 sx |
| 廠商： | Intel Corp. |
| 英文描述： | SX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
| 中文描述： | 山西數(shù)學(xué)協(xié)處理器（32位數(shù)學(xué)協(xié)處理器） |
| 文件頁數(shù)： | 30/47頁 |
| 文件大小： | 443K |
| 代理商： | INTEL387 SX |
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Intel387
TM
SX MATH COPROCESSOR
during the transitions to or from that state, the only
difference between a pipelined and a non-pipelined
cycle is the manner of changing from one state to
another. The exact activities during each state are
detailed in the previous section ‘‘Non-pipelined Bus
Cycles’’.
When the CPU asserts ADS
Y
before the end of a
bus cycle, both ADS
Y
and READY
Y
are active dur-
ing a T
RS
state. This condition causes the Math Co-
Processor to change to a different state named T
P
.
One clock period after a T
P
state, the Math CoProc-
essor always returns to the T
RS
state. In consecu-
tive pipelined cycles, the Math CoProcessor bus log-
ic uses only the T
RS
and T
P
states.
Figure 5-3 shows the fastest transitions into and out
of the pipelined bus cycles. Cycle 1 in the figure rep-
resents a non-pipelined cycle. (Non-pipelined write
are always followed by another non-pipelined cycle,
because READY
Y
is asserted before the earliest
possible assertion of ADS
Y
for the next cycle.)
Figure 5-4 shows pipelined write and read cycles
with one additional T
RS
state beyond the minimum
required. To delay the assertion of READY
Y
re-
quires external logic.
5.3 Mixed Bus Cycles
When the Math CoProcessor bus logic is in the T
RS
state, it distinguishes between non-pipelined and
pipelined cycles according to the behavior of ADS
Y
and READY
Y
. In a non-pipelined cycle, only
READY
Y
is activated, and the transition is from the
T
RS
state to the idle state. In a pipelined cycle, both
READY
Y
and ADS
Y
are active, and the transition is
first from T
RS
state to T
P
state, then, after one clock
period, back to T
RS
state.
240225–9
Cycle 1–Cycle 4 represent the operand transfer cycle for an instruction involving a transfer of two 32-bit loads in total.
The opcode write cycles and other overhead are not shown.
Note that the next cycle will be a pipelined cycle if both READY
Y
and ADS
Y
are sampled active at the end of a T
RS
state of the current cycle.
Figure 5-3. Fastest Transitions to and from Pipelined Cycles
30
30
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| INTEL486 GX | Emedded Ultra-Low Power INTEL486 GX Processor(嵌入式超低能量處理器) |
| INTEL486 SX | Emedded Ultra-Low Power INTEL486 SX Processor(嵌入式超低能量處理器) |
| INTEL82801 | 82801AB (ICH0) I/O Controller Hub |
| INTEL82802AB | Firmware Hub (FWH) |
| INTELDX2 | High-Performance 32-Bit Embedded Processor(高性能32位嵌入式處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
| INTEL740 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Graphics (GUI) Accelerator |
| INTEL82801 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:82801AB (ICH0) I/O Controller Hub |
| INTEL82802AB | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Firmware Hub (FWH) |
| INTELLIGENT CHARGER + 4AA | 制造商:Energizer 功能描述:Bulk |
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