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參數(shù)資料
| 型號： | Intel387 sx |
| 廠商： | Intel Corp. |
| 英文描述： | SX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
| 中文描述： | 山西數(shù)學(xué)協(xié)處理器（32位數(shù)學(xué)協(xié)處理器） |
| 文件頁數(shù)： | 26/47頁 |
| 文件大小： | 443K |
| 代理商： | INTEL387 SX |
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Intel387
TM
SX MATH COPROCESSOR
4.3 Math CoProcessor Architecture
As shown in Figure 2-1 Block Diagram, the Intel387
SX Math CoProcessor is internally divided into four
sections; the Bus Control Logic (BCL), the Data In-
terface and Control Logic, the Floating Point Unit
(FPU), and the Power Management Unit (PMU). The
Bus Control Logic is responsible for the CPU bus
tracking and interface. The BCL is the only unit in
the Math CoProcessor that must run synchronously
with the CPU; the rest of the Math CoProcessor can
run asynchronously with respect to the CPU. The
Data Interface and Control Unit is responsible for the
data flow to and from the FPU and the control regis-
ters, for receiving the instructions, decoding them,
sequencing the microinstructions, and for handling
some of the administrative instructions. The Floating
Point Unit (with the support of the control unit which
contains the sequencer and other support units) ex-
ecutes the mathematical instructions. The Power
Manager is new to the Intel387 family. It is responsi-
ble for shutting down idle sections of the device to
save power.
4.3.1 BUS CONTROL LOGIC
The BCL communicates solely with the CPU using
I/O bus cycles. The BCL appears to the CPU as a
special peripheral device. It is special in two re-
spects: the CPU initiates I/O automatically when it
encounters ESC instructions, and the CPU uses re-
served I/O addresses to communicate with the BCL.
The BCL does not communicate directly with memo-
ry. The CPU performs all memory access, transfer-
ring input operands from the memory to the Math
CoProcessor and transferring outputs from the Math
CoProcessor to memory.
4.3.2 DATA INTERFACE AND CONTROL UNIT
The data interface and control unit latches the data
and, subject to BCL control, directs the data to the
FIFO or the instruction decoder. The instruction de-
coder decodes the ESC instructions sent to it by the
CPU and generates controls that direct the data flow
in the FIFO. It also triggers the microinstruction se-
quencer that controls execution of each instruction.
If the ESC instruction is FINIT, FCLEX, FSTSW,
FSTSW AX, FSTCW, FSETPM, or FRSTPM, the
control unit executes it independently of the FPU
and the sequencer. The data interface and control
unit is the unit that generates the BUSY
Y
, PEREQ,
and ERROR
Y
signals that synchronize the Math
CoProcessor activities with the CPU.
4.3.3 FLOATING POINT UNIT
The FPU executes all instructions that involve the
register stack, including arithmetic, logical, transcen-
dental, constant, and data transfer instructions. The
data path in the FPU is 84 bits wide (68 significant
bits, 15 exponent bits, and a sign bit) which allows
internal operand transfers to be performed at very
high speeds.
4.3.4 POWER MANAGEMENT UNIT
The Power Management Unit (PMU) controls all in-
ternal power savings circuits. When the Math Co-
Processor is not executing an instruction, the PMU
disables the internal clock to the FPU, Control Unit,
and Data Interface within three clocks. The Bus
Control Logic remains enabled to accept the next
instruction. Upon decode of a valid Math CoProces-
sor bus cycle, the PMU enables the internal clock to
all circuits. No loss in performance occurs.
4.4 Bus Cycles
All bus cycles are initiated by the CPU. The pins
STEN, NPS1
Y
, NPS2, CMD0, and W/R
Y
identify
bus cycles for the Math CoProcessor. Table 4-3 de-
fines the types of Math CoProcessor bus cycles.
Table 4-3. Bus Cycle Definition
STEN
NPS1
Y
NPS2
CMD0
Y
W/R
Y
Bus Cycle Type
0
1
1
1
1
1
1
X
1
X
0
0
0
0
X
X
0
1
1
1
1
X
X
X
0
0
1
1
X
X
X
0
1
0
1
Math CoProcessor not selected and all outputs in floating state
Math CoProcessor not selected
Math CoProcessor not selected
CW or SW read from Math CoProcessor
Opcode write to Math CoProcessor
Data read from Math CoProcessor
Data write to Math CoProcessor
26
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