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參數(shù)資料
| 型號(hào)： | INTEL486 GX |
| 廠商： | Intel Corp. |
| 英文描述： | Emedded Ultra-Low Power INTEL486 GX Processor(嵌入式超低能量處理器) |
| 中文描述： | Emedded超低功耗英特爾486 GX處理器（嵌入式超低能量處理器） |
| 文件頁(yè)數(shù)： | 1/48頁(yè) |
| 文件大小： | 409K |
| 代理商： | INTEL486 GX |
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INTEL CORPORATION, 1997
December 1997
Order Number:
272755-002
EMBEDDED ULTRA-LOW POWER Intel486
GX PROCESSOR
Figure 1.
Embedded Ultra-Low Power Intel486 GX Processor Block Diagram
I
Ultra-Low Power Member of the Intel486
Processor Family
— 32-Bit RISC Technology Core
— 8-Kbyte Write-Through Cache
— Four Internal Write Buffers
— Burst Bus Cycles
— Data Bus Parity Generation and
Checking
— Intel System Management Mode (SMM)
— Boundary Scan (JTAG)
I
16-Bit External Data Bus
I
176-Lead Thin Quad Flat Pack (TQFP)
I
Separate Voltage Supply for Core Circuitry
I
Fast Core-Clock Restart
I
Auto Clock Freeze
I
Ideal for Embedded Battery-Operated and
Hand-Held Applications
A5851-01
Paging
Unit
Prefetcher
32-Byte Code
Queue
2x16 Bytes
Code
Stream
Barrel
Shifter
Cache Unit
Burst Bus
Control
Bus Control
Write Buffers
4 x 32
64-Bit Interunit Transfer Bus
Register
File
ALU
Segmentation
Unit
Descriptor
Registers
Limit and
Attribute PLA
Base/
Index
Bus
32
Translation
Lookaside
Buffer
8 Kbyte
Cache
Clock
Control
Control &
Protection
Test Unit
Control
ROM
Address
Drivers
CLK Input
Core
Clock
Data Bus
Transceivers
Request
Sequencer
Cache
Control
Parity
Generation
and Control
Boundary
Scan
Control
Bus Interface
D15-D0
A31-A2
BE3#- BE0#
ADS# W/R# D/C# M/IO#
PCD PWT RDY# LOCK#
PLOCK# BOFF# A20M#
BREQ HOLD HLDA
RESET SRESET INTR
NMI SMI# SMIACT#
STPCLK#
BRDY# BLAST#
KEN# FLUSH#
AHOLD EADS#
DP1-DP0, PCHK#
TCK TMS
TDI TD0
Instruction
Decode
Decoded
PCD
PWT
2
Physical
Address
32-Bit Data Bus
32-Bit Data Bus
Linear Address
InMicro-
Displacement Bus
32
32
32
32
128
32
32
32
20
24
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