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Contents
iv
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Address Prediction for Burst Transfers (1 of 3) ........................................................................25
Address Prediction for Burst Transfers (2 of 3) ........................................................................26
Address Prediction for Burst Transfers (3 of 3) ........................................................................27
CLK Waveform .........................................................................................................................37
Input Setup and Hold Timing ...................................................................................................37
Input Setup and Hold Timing ...................................................................................................38
Output Valid Delay Timing .......................................................................................................38
PCHK# Valid Delay Timing ......................................................................................................39
Maximum Float Delay Timing ..................................................................................................39
TCK Waveform ........................................................................................................................40
Test Signal Timing Diagram .....................................................................................................40
Typical Loading Delay versus Load Capacitance under Worst-Case Conditions
for a Low-to-High Transition .....................................................................................................41
Typical Loading Delay versus Load Capacitance under Worst-Case Conditions
for a High-to-Low Transition .....................................................................................................41
Package Mechanical Specifications for the 176-Lead TQFP Package ....................................42
Figure 18.
Figure 19.
TABLES
Table 1.
Table 2.
Table 3.
The Embedded Ultra-Low Power Intel486
GX Processor .......................................................3
Pin Assignment for 176-Lead TQFP Package Embedded ULP Intel486 GX Processor ........5
Pin Cross Reference for 176-Lead TQFP Package Embedded ULP
Intel486 GX Processor ...........................................................................................................6
Embedded ULP Intel486 GX Processor Pin Descriptions ......................................................7
Output Pins ..............................................................................................................................13
Input/Output Pins .....................................................................................................................13
Test Pins ..................................................................................................................................14
Input Pins .................................................................................................................................14
Valid Byte-Enable Cycles .........................................................................................................20
Address Sequence for Cache Line Transfers and Instruction Prefetches ...............................22
Valid Burst Cycle Sequences - I/O Reads and All Writes ........................................................23
CPUID Instruction Description .................................................................................................28
Boundary Scan Component Identification Code ......................................................................29
Absolute Maximum Ratings .....................................................................................................30
Operating Supply Voltages ......................................................................................................31
DC Specifications .....................................................................................................................31
Active I
CC
Values .....................................................................................................................32
Clock Stop, Stop Grant, and Auto HALT Power Down I
CC
Values ..........................................33
AC Characteristics ...................................................................................................................34
AC Specifications for the Test Access Port .............................................................................36
Thermal Resistance .................................................................................................................43
Maximum Ambient Temperature (T
A
) ......................................................................................43
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.