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參數(shù)資料
| 型號(hào)： | INTEL486 GX |
| 廠商： | Intel Corp. |
| 英文描述： | Emedded Ultra-Low Power INTEL486 GX Processor(嵌入式超低能量處理器) |
| 中文描述： | Emedded超低功耗英特爾486 GX處理器（嵌入式超低能量處理器） |
| 文件頁數(shù)： | 27/48頁 |
| 文件大?。?/td> | 409K |
| 代理商： | INTEL486 GX |
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23
Embedded Ultra-Low Power Intel486 GX Processor
Whenever its cache circuitry is not busy, the
processor uses this same bursting mechanism for
prefetching instructions (128 bits, 16 bytes), even if
the instructions are not indicated as cacheable by
the external system. Instruction prefetches can occur
that use the address sequencing shown in Table 10.
The initial value of A31-A4, M/IO#, W/R#, and D/C#
are presented by the processor throughout the 128-
bit prefetch burst. It is possible for the processor to
prefetch instructions not needed. The burst
sequence can be terminated by the processor at any
time with an active BLAST# signal.
4.5.3.3 Non-Cacheable Cycles
For memory and I/O data transfers, the embedded
ULP Intel486 GX processor determines how many
data cycles are required for the transfer based on its
internal information. This information includes the
byte-length of the data, the transfer’s starting data
address, and data alignment. For memory reads, the
processor resorts to the 128-bit cache-line address
sequence described above if the external system
indicates the data is cacheable. Otherwise, the
processor uses its internal information to determine
whether to burst the data cycles of a multiple-cycle
transfer. In some cases, the transfer can be
performed entirely by burst cycles. In other cases, a
combination of burst cycles and single cycles are
required to perform the data transfer. There are also
cases for which burst cycles cannot be used and the
transfer consists of multiple cycles, each beginning
with the ADS# signal.
I/O Writes, I/O Reads, and Memory Writes
If the processor initiates bursting (BLAST# inactive)
during an I/O Write, I/O Read or Memory Write, the
duration of the burst is a maximum of four bytes (32
bits). All of the possible burst situations are listed in
Table 11. In all cases, the burst is two data cycles.
The control signals M/IO#, D/C#, W/R#, address bits
A31-A4 as well as A3 and A2 remain constant
throughout each two-cycle burst.
Table 11. Valid Burst Cycle Sequences - I/O Reads and All Writes
Starting Address
(Least significant
hexadecimal digit)
Data
Cycle
Signals from the Processor
Address of
Expected Read Data
A3 A2
Byte Enables
BE3#-BE0#
A3-A0
(Hex)
BLAST#
D15-D8,
DP1
D7-D-0,
DP0
0, 4, 8, C
1
A3 A2
0 0 0 0
0, 4, 8, C
1
2nd
1st
2
A3 A2
0 0 1 1
2, 6, A, E
0
4th
3rd
1, 5, 9, D
1
A3 A2
0 0 0 1
1, 5, 9, D
1
1st
-
2
A3 A2
0 0 1 1
2, 6, A, E
0
3rd
2nd
1, 5, 9, D
1
A3 A2
1 0 0 1
1, 5, 9, D
1
1st
-
2
A3 A2
1 0 1 1
2, 6, A, E
0
-
2nd
2, 6, A, E
1
A3 A2
1 0 0 0
0, 4, 8, C
1
2nd
1st
2
A3 A2
1 0 1 1
2, 6, A, E
0
-
3rd
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