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參數(shù)資料
| 型號： | INTEL486 GX |
| 廠商： | Intel Corp. |
| 英文描述： | Emedded Ultra-Low Power INTEL486 GX Processor(嵌入式超低能量處理器) |
| 中文描述： | Emedded超低功耗英特爾486 GX處理器（嵌入式超低能量處理器） |
| 文件頁數(shù)： | 22/48頁 |
| 文件大?。?/td> | 409K |
| 代理商： | INTEL486 GX |
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Embedded Ultra-Low Power Intel486 GX Processor
18
The embedded ULP Intel486 GX processor’s data
bus pins (D15-D0) and data parity pins have level
keepers which maintain their previous states while in
the Stop Grant and Stop Clock states. In response to
HOLD driven active during the Stop Grant state
when the CLK input is running, the embedded ULP
Intel486 GX processor generates HLDA and floats
D15-D0, DP1 and DP0 throughout the HOLD/HLDA
cycles. When HOLD is deasserted, the processor’s
D15-D0, DP1 and DP0 signals return to the states
they were in prior to the HOLD/HLDA sequence.
At all other times during the Stop Grant and Stop
Clock states, the processor maintains the logic
levels of D15-D0, DP1 and DP0. When the external
system circuitry drives D15-D0, DP1 and DP0 to
different logic levels, the processor flips its D15-D0,
DP1 and DP0 logic levels to match the ones driven
by the external system. The processor maintains
(keeps) these new levels even after the external
circuitry stops driving D15-D0, DP1 and DP0.
For some system designs, external resistors may not
be required on D15-D0, DP1 and DP0 (they are
required on previous Intel486 SX processor
designs). System designs that never request Bus
Hold during the Stop Grant and Stop Clock states
might not require external resistors. If the system
design uses Bus Hold during these states, the
processor disables the level-keepers and floats the
data bus. This type of design would require some
kind of data bus termination to minimize power
consumption. It is strongly recommended that the
D15-D0, DP1 and DP0 pins do not have network
resistors connected. External resistors used in the
system design must be of a sufficient resistance
value to “flip” the level-keeper circuitry and eliminate
potential DC paths.
The level-keeper circuits for DP1 and DP0 are
always enabled, while the level-keeper circuits for
D15-D0 are enabled only during the Stop Grant and
Stop Clock states.
The level-keeper circuit is designed to allow an
external 27-K
pull-up resistor to switch the D15-D0,
DP1 and DP0 circuits to a logic-HIGH level even
though the level-keeper attempts to keep a logic-
LOW level. In general, pull-up resistors smaller than
27 K
can be used as well as those greater than or
equal to 1 M
. Pull-down resistors, when connected
to D15-D0, DP1 and DP0, should be least 800 K
.
4.4
Low-Power Features
As with other Intel486 processors, the embedded
ULP Intel486 GX processor minimizes power
consumption by providing the Auto HALT Power
Down, Stop Grant, and Stop Clock states (see
Figure 4). The embedded ULP Intel486 GX
processor has an Auto Clock Freeze feature that
further conserves power by judiciously deactivating
its internal clocks while in the Normal Execution
Mode.
The
power-conserving
designed such that it does not degrade processor
performance or require changes to AC timing specifi-
cations.
mechanism
is
4.4.1
Auto Clock Freeze
To reduce power consumption, during the following
bus cycles — under certain conditions — the
processor slows-up or freezes some internal clocks:
Data-Read Wait Cycles (Memory, I/O and Interrupt
Acknowledge)
Data-Write Wait Cycles (Memory, I/O)
HOLD/HLDA Cycles
AHOLD Cycles
BOFF Cycles
Power is conserved during the wait periods in these
cycles until the appropriate external-system signals
are sent to the processor. These signals include:
READY
NMI, SMI#, INTR, and RESET
BOFF#
FLUSH#
EADS#
KEN# transitions
The embedded ULP Intel486 GX processor also
reduces power consumption by temporarily freezing
the clocks of its internal logic blocks. When a logic
block is idle or in a wait state, its clock is frozen.
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