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參數資料
| 型號： | INTEL486 GX |
| 廠商： | Intel Corp. |
| 英文描述： | Emedded Ultra-Low Power INTEL486 GX Processor(嵌入式超低能量處理器) |
| 中文描述： | Emedded超低功耗英特爾486 GX處理器（嵌入式超低能量處理器） |
| 文件頁數： | 20/48頁 |
| 文件大?。?/td> | 409K |
| 代理商： | INTEL486 GX |
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Embedded Ultra-Low Power Intel486 GX Processor
16
Even though V
must be less than or equal to
V
, it is recommended that the system’s power-on
sequence allows V
CC
to quickly achieve its opera-
tional level once V
achieves its operational level.
Similarly, the power-down sequence should allow
V
to power down quickly after V
CC
is below the
operational voltage level.
These recommendations are given to keep power
consumption at a minimum. Deviating from the
recommendations does not create a component
reliability problem, but power consumption of the
processor’s external interface circuits increases
beyond normal operating values.
Figure 3. Example of Supply Voltage Power Sequence
4.2
Fast Clock Restart
The embedded ULP Intel486 GX processor has an
integrated proprietary differential delay line (DDL)
circuit for internal clock generation. The DDL is
driven by the CLK input signal provided by the
external system. During normal operation, the
external system must guarantee that the CLK signal
maintains its frequency so that the clock period
deviates no more than 250 ps/CLK. This state,
called the Normal State, is shown in Figure 4.
To increase or decrease the CLK frequency more
quickly than this, the system must interrupt the
processor with the STPCLK# signal. Once the
processor indicates that it is in the Stop Grant State,
the system can adjust the CLK signal to the new
frequency, wait a minimum of eight CLK periods,
then force the processor to return to the normal
operational state by deactivating the STPCLK#
interrupt. This wait of eight CLK periods is much
faster than the 1 ms wait required by earlier Intel486
SX processor products.
While in the Stop Grant State, the external system
may deactivate the CLK signal to the processor. This
forces the processor to the Stop Clock State — the
state in which the processor consumes the least
power. Once the system reactivates the CLK signal,
the processor transitions to the Stop Grant State
within eight CLK periods.
Normal operation can be resumed by deactivating
the STPCLK# interrupt signal. Here again, the
embedded ULP Intel486 GX processor recovers
from the Stop Clock State much faster than the 1 ms
PLL recovery of earlier Intel486 SX processors.
TIME
V
CCP
V
CC
0 V
V
CC
min
V
CCP
min
V
CC
and V
CCP
(V)
POWER OFF
POWER ON
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