參數(shù)資料
型號： INTEL486 GX
廠商： Intel Corp.
英文描述： Emedded Ultra-Low Power INTEL486 GX Processor(嵌入式超低能量處理器)
中文描述： Emedded超低功耗英特爾486 GX處理器（嵌入式超低能量處理器）
文件頁數(shù)： 15/48頁
文件大?。?/td> 409K
代理商： INTEL486 GX
Embedded Ultra-Low Power Intel486 GX Processor
11
HLDA
O
Hold Acknowledge
goes active in response to a hold request presented on the
HOLD pin. HLDA indicates that the embedded ULP Intel486 GX processor has
given the bus to another local bus master. HLDA is driven active in the same clock
that the processor floats its bus. HLDA is driven inactive when leaving bus hold.
HLDA is active HIGH and remains driven during bus hold.
Backoff
nput forces the embedded ULP Intel486 GX processor to float its bus in
the next clock. The processor floats all pins normally floated during bus hold but
HLDA is not asserted in response to BOFF#. BOFF# has higher priority than RDY#
or BRDY#; if both are returned in the same clock, BOFF# takes effect. The
embedded ULP Intel486 GX processor remains in bus hold until BOFF# is
negated. If a bus cycle is in progress when BOFF# is asserted the cycle is
restarted. BOFF# is active LOW and must meet setup and hold times t
18
and t
19
for
proper operation.
BOFF#
I
CACHE INVALIDATION
AHOLD
I
Address Hold
request allows another bus master access to the embedded ULP
Intel486 GX processor
’s address bus for a cache invalidation cycle. The processor
stops driving its address bus in the clock following AHOLD going active. Only the
address bus is floated during address hold, the remainder of the bus remains
active. AHOLD is active HIGH and is provided with a small internal pull-down
resistor. For proper operation, AHOLD must meet setup and hold times t
18
and t
19
.
External Address
- This signal indicates that a
valid
external address has been
driven onto the embedded ULP Intel486 GX processor address pins. This address
is used to perform an internal cache invalidation cycle. EADS# is active LOW and
is provided with an internal pull-up resistor. EADS# must satisfy setup and hold
times t
12
and t
13
for proper operation.
EADS#
I
CACHE CONTROL
KEN#
I
Cache Enable
pin is used to determine whether the current cycle is cacheable.
When the embedded ULP Intel486 GX processor generates a cycle that can be
cached and KEN# is active one clock before RDY# or BRDY# during the first
transfer of the cycle, the cycle becomes a cache line fill cycle. Returning KEN#
active one clock before RDY# during the last read in the cache line fill causes the
line to be placed in the on-chip cache. KEN# is active LOW and is provided with a
small internal pull-up resistor. KEN# must satisfy setup and hold times t
14
and t
15
for proper operation.
Cache Flush
input forces the embedded ULP Intel486 GX processor to flush its
entire internal cache. FLUSH# is active LOW and need only be asserted for one
clock. FLUSH# is asynchronous but setup and hold times t
20
and t
21
must be met
for recognition in any specific clock.
FLUSH#
I
Table 4. Embedded ULP Intel486
GX Processor Pin Descriptions
(Sheet 5 of 6)
Symbol
Type
Name and Function
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