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參數(shù)資料
| 型號： | INTEL486 GX |
| 廠商： | Intel Corp. |
| 英文描述： | Emedded Ultra-Low Power INTEL486 GX Processor(嵌入式超低能量處理器) |
| 中文描述： | Emedded超低功耗英特爾486 GX處理器（嵌入式超低能量處理器） |
| 文件頁數(shù)： | 28/48頁 |
| 文件大?。?/td> | 409K |
| 代理商： | INTEL486 GX |
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Embedded Ultra-Low Power Intel486 GX Processor
24
Non-Cacheable Memory Reads
When the processor initiates bursting, the duration of
the burst is a maximum of 16 bytes (128 bits).
Non-cacheable instruction prefetches can be 16
bytes in duration. The possible burst sequences are
the same as for cache-line transfers listed in Table
11. The burst sequence can be terminated at any
time with an active BLAST# signal.
The length of a burst transfer can be 16, eight, or
fewer than eight bytes.
For burst lengths of eight or less, the entire burst
transfer is confined to a quad-word (eight-byte) data
boundary of system memory. A31-A3 remain
constant throughout this type of burst transfer.
4.5.3.4 Burst Transfer Address Prediction
The processor provides the data address (A31-A2)
and byte enables (BE3#-BE0#) for the first data
cycle while ADS# is inactive. The initial values for
A1, BHE# and BLE# (A0) can be derived from the
byte enables. If bursting is anticipated, the next data
address can be predicted at this time and can be
used by the memory controller to perform burst data
transfers with minimal wait states. Rather than list all
of the burst mode address combinations, a general
algorithm is provided in Figure 6. This algorithm
holds true for all burst transfers including cache-line
fills, instruction prefetches, I/O and memory-write
data transfers described in earlier sections.
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