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參數(shù)資料
| 型號： | INTEL486 GX |
| 廠商： | Intel Corp. |
| 英文描述： | Emedded Ultra-Low Power INTEL486 GX Processor(嵌入式超低能量處理器) |
| 中文描述： | Emedded超低功耗英特爾486 GX處理器（嵌入式超低能量處理器） |
| 文件頁數(shù)： | 24/48頁 |
| 文件大?。?/td> | 409K |
| 代理商： | INTEL486 GX |
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Embedded Ultra-Low Power Intel486 GX Processor
20
Table 9 contains the list of valid byte-enable combinations and how the 16-bit external data bus is interpreted.
Table 9. Valid Byte-Enable Cycles
Case
Byte Enables
From External Circuitry
(Note 1)
External Data
Bus
BE3#
BE2#
BE1#
BE0#
A1
A0
BHE#
BLE#
(A0)
D15-
D8, DP1
D7-D0,
DP0
1
1
1
1
0
0
0
1
0
-
valid
2
1
1
0
0
0
0
0
0
valid
valid
3
1
0
0
0
0
0
0
0
valid
valid
4
0
0
0
0
0
0
0
0
valid
valid
5
1
1
0
1
0
1
0
1
valid
-
6
1
0
0
1
0
1
0
1
valid
-
7
0
0
0
1
0
1
0
1
valid
-
8
1
0
1
1
1
0
1
0
-
valid
9
0
0
1
1
1
0
0
0
valid
valid
10
0
1
1
1
1
1
0
1
valid
-
NOTES:
1. If the external system indicates to the processor that a read is cacheable, the processor initiates a cache-
line fill. In this case, the external system should ignore BE3#, BE2#, BE1#, and BE0# and force A1, A0, and
BHE# to a low logic level (0) for the first cycle of the transfer. This forces a memory read to start from a data
address having its least significant digit 0, 4, 8, or C (hex). The byte-enable decodes for subsequent cycles
of the line fill follow the table information as listed.
Except for the initial transfer of a cache-line fill, the
Byte Enables BE3#, BE2#, BE1#, and BE0# for
cases 1, 2, 5, 8, 9, and 10 indicate either a one-, or
two-byte data transfer that can be accomplished in
one 16-bit data cycle.
Except for the initial transfer of a cache-line fill, the
Byte Enables BE3#, BE2#, BE1#, and BE0# for
cases 3, 4, 6, and 7 indicate the transfer of two,
three, or four data bytes that cannot be accom-
plished in one 16-bit data cycle. In these cases, the
processor attempts to complete the partial transfer
using an additional data cycle. The additional cycle
could be burst by the processor (processor could
respond with BLAST# unasserted for case 3, 4, 6, or
7). This is true for both memory and I/O reads and
writes. There is more information about bursting in
later sections.
During write cycles, valid data is only driven onto the
external data bus pins corresponding to active byte
enables. Other pins of the data bus are driven but do
not contain valid data.
NOTE:
Unlike the Intel386
processor, the
embedded ULP Intel486 GX processor
does not duplicate write data onto the parts
of the data bus for which the corre-
sponding byte enable is inactive.
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