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參數(shù)資料
| 型號： | Intel387 sx |
| 廠商： | Intel Corp. |
| 英文描述： | SX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
| 中文描述： | 山西數(shù)學(xué)協(xié)處理器（32位數(shù)學(xué)協(xié)處理器） |
| 文件頁數(shù)： | 13/47頁 |
| 文件大?。?/td> | 443K |
| 代理商： | INTEL387 SX |
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Intel387
TM
SX MATH COPROCESSOR
Table 3-1. Condition Code Interpretation
Instruction
C0 (S)
C3 (Z)
C1 (A)
C2 (C)
FPREM, FPREM1
(see Table 3-2)
Three least significant bits
of quotient
Reduction
0
e
complete
1
e
incomplete
Q2
Q0
Q1
or O/U
Y
FCOM, FCOMP,
FCOMPP, FTST,
FUCOM, FUCOMP,
FUCOMPP, FICOM,
FICOMP
Result of comparison
(see Table 3-3)
Zero
or O/U
Y
Operand is not
comparable
(Table 3-3)
FXAM
Operand class
(see Table 3-4)
Sign
Operand class
(Table 3-4)
or O/U
Y
FCHS, FABS, FXCH,
FINCSTP, FDECSTP,
Constant loads,
FXTRACT, FLD,
FILD, FBLD,
FSTP (ext real)
Zero
or O/U
Y
UNDEFINED
UNDEFINED
FIST, FBSTP,
FRNDINT, FST,
FSTP, FADD, FMUL,
FDIV, FDIVR,
FSUB, FSUBR,
FSCALE, FSQRT,
FPATAN, F2XM1,
FYL2X, FYL2XP1
Roundup
or O/U
Y
UNDEFINED
UNDEFINED
FPTAN, FSIN
FCOS, FSINCOS
Roundup
or O/U
Y
,
undefined
if C2
e
1
Reduction
0
e
complete
1
e
incomplete
UNDEFINED
FLDENV, FRSTOR
Each bit loaded from memory
FLDCW, FSTENV,
FSTCW, FSTSW,
FCLEX, FINIT,
FSAVE
UNDEFINED
O/U
Y
When both IE and SF bits of status word are set, indicating a stack exception, this bit
distinguishes between stack overflow (C1
e
1) and underflow (C1
e
0).
If FPREM or FPREM1 produces a remainder that is less than the modulus, reduction is
complete. When reduction is incomplete the value at the top of the stack is a partial
remainder, which can be used as input to further reduction. For FPTAN, FSIN, FCOS, and
FSINCOS, the reduction bit is set if the operand at the top of the stack is too large. In this
case the original operand remains at the top of the stack.
Reduction
Roundup
When the PE bit of the status word is set, this bit indicates whether the last rounding in the
instruction was upward.
UNDEFINED
Do not rely on finding any specific value in these bits.
13
13
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