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參數(shù)資料
| 型號(hào)： | Intel387 sx |
| 廠商： | Intel Corp. |
| 英文描述： | SX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
| 中文描述： | 山西數(shù)學(xué)協(xié)處理器（32位數(shù)學(xué)協(xié)處理器） |
| 文件頁(yè)數(shù)： | 25/47頁(yè) |
| 文件大?。?/td> | 443K |
| 代理商： | INTEL387 SX |
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Intel387
TM
SX MATH COPROCESSOR
4.2 System Configuration
The Intel387 SX Math CoProcessor is designed to
interface with the Intel386 SX Microprocessor as
shown by Figure 4-1. A dedicated communication
protocol makes possible high-speed transfer of op-
codes and operands between the CPU and Math
CoProcessor. The Intel387 SX Math CoProcessor is
designed so that no additional components are re-
quired for interface with the CPU. Most control pins
of the Math CoProcessor are connected directly to
pins of the CPU.
The interface between the Math CoProcessor and
the CPU has these characteristics:
#
The Math CoProcessor shares the local bus of
the Intel386 SX Microprocessor.
#
The CPU and Math CoProcessor share the same
reset signals. They may also share the same
clock input; however, for greatest performance,
an external oscillator may be needed.
Busy
Y
,
PEREQ pins are connected together.
The Math CoProcessor NPS1
Y
and NPS2 inputs
are connected to the latched CPU M/IO
Y
and
A23 outputs respectively. For Math CoProcessor
cycles, M/IO
Y
is always LOW and A23 always
HIGH.
#
The
corresponding
ERROR
Y
,
and
#
#
The Math CoProcessor input CMD0 is connected
to the latched A
2
output. The Intel386 SX Micro-
processor generates address 8000F8H when
writing a command and address 8000FCH or
8000FEH (treated as 8000FCH by the Intel387
SX Math CoProcessor) when writing or reading
data. It does not generate any other addresses
during Math CoProcessor bus cycles.
240225–6
Figure 4-1. Intel386
TM
SX CPU and Intel387
TM
SX Math CoProcessor System Configuration
25
25
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| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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