參數(shù)資料
型號(hào)： Intel387 sx
廠商： Intel Corp.
英文描述： SX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器)
中文描述： 山西數(shù)學(xué)協(xié)處理器（32位數(shù)學(xué)協(xié)處理器）
文件頁數(shù)： 4/47頁
文件大?。?/td> 443K
代理商： INTEL387 SX
CONTENTS
PAGE
FIGURES
Figure 1-1
Intel387 SX Math
CoProcessor Pinout
ààààààààààà 5
Intel387 SX Math
CoProcessor Block
Diagram
àààààààààààààààààààààà 7
Intel 386 SX CPU and
Intel387 Math CoProcessor
Register Set
ààààààààààààààààà 11
Status Word
ààààààààààààààààà 12
Control Word
àààààààààààààààà 15
Tag Word Register
ààààààààààà 16
Instruction and Data Pointer
Image in Memory, 32-Bit
Protected Mode Format
àààààà 17
Instruction and Data Pointer
Image in Memory, 16-Bit
Protected Mode Format
àààààà 17
Instruction and Data Pointer
Image in Memory, 32-Bit
Real Mode Format
ààààààààààà 17
Instruction and Data Pointer
Image in Memory, 16-Bit
Real Mode Format
ààààààààààà 18
Intel386 SX CPU and
Intel387 SX Math
CoProcessor System
Configuration
àààààààààààààààà 25
Bus State Diagram
ààààààààààà 28
Non-Pipelined Read and
Write Cycles
ààààààààààààààààà 29
Fastest Transition to and
from Pipelined Cycles
àààààààà 30
Pipelined Cycles with Wait
States
ààààààààààààààààààààààà 31
BUSY
Y
and PEREQ Timing
Relationship
ààààààààààààààààà 32
Figure 7-1a Typical Output Valid Delay
vs Load Capacitance at Max
Operating Temperature
àààààà 37
Figure 7-1b Typical Output Slew Time vs
Load Capacitance at Max
Operating Temperature
àààààà 37
Figure 7-1c Maximum I
CC
vs
Frequency
ààààààààààààààààààà 37
Figure 2-1
Figure 3-1
Figure 3-2
Figure 3-3
Figure 3-4
Figure 3-5
Figure 3-6
Figure 3-7
Figure 3-8
Figure 4-1
Figure 5-1
Figure 5-2
Figure 5-3
Figure 5-4
Figure 5-5
CONTENTS
Figure 7-2
PAGE
CPUCLK2/NUMCLK2
Waveform and
Measurement Points for
Input/Output
ààààààààààààààààà 38
Output Signals
ààààààààààààààà 38
Input and I/O Signals
àààààààà 39
RESET Signal
àààààààààààààààà 39
Float from STEN
ààààààààààààà 40
Other Parameters
àààààààààààà 40
Figure 7-3
Figure 7-4
Figure 7-5
Figure 7-6
Figure 7-7
TABLES
Table 1-1
Pin Cross ReferenceD
Functional Grouping
ààààààààààà 5
Condition Code
Interpretation
ààààààààààààààààà 13
Condition Code Interpretation
after FPREM and FPREM1
Instructions
ààààààààààààààààààà 14
Condition Code Resulting
from Comparison
ààààààààààààà 14
Condition Code Defining
Operand Class
ààààààààààààààà 14
Mapping Condition Codes to
Intel386 CPU Flag Bits
àààààààà 14
Intel387 SX Math
CoProcessor Data Type
Representation in Memory
àààà 19
CPU Interrupt Vectors
Reserve for Math
CoProcessor
ààààààààààààààààà 20
Intel387 SX Math
CoProcessor Exceptions
àààààà 20
Pin Summary
ààààààààààààààààà 22
Output Pin Status during
Reset
àààààààààààààààààààààààà 23
Bus Cycle Definition
àààààààààà 26
Thermal Resistances
(
§
C/Watt)
i
JC
and
i
JA
àààààààà 33
Maximum T
A
at Various
Airflows
àààààààààààààààààààààà 33
D.C. Specifications
ààààààààààà 34
Table 7-2a Timing Requirements of the
Bus Interface Unit
àààààààààààà 35
Table 7-2b Timing Requirements of the
Execution Unit
àààààààààààààààà 36
Table 7-2c Other AC Parameters
ààààààààà 36
Table 8-1
Instruction Formats
ààààààààààà 41
Table 3-1
Table 3-2
Table 3-3
Table 3-4
Table 3-5
Table 3-6
Table 3-7
Table 3-8
Table 4-1
Table 4-2
Table 4-3
Table 6-1
Table 6-2
Table 7-1
4
4
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