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Intel387
TM
SX MATH COPROCESSOR
Table 3-7. CPU Interrupt Vectors Reserved for Math CoProcessor
Interrupt
Number
Cause of Interrupt
7
An ESC instruction was encountered when EM or TS of CPU control register zero (CR0) was
set. EM
e
1 indicates that software emulation of the instruction is required. When TS is set,
either an ESC or WAIT instruction causes interrupt 7. This indicates that the current Math
CoProcessor context may not belong to the current task.
9
In a protected-mode system, an operand of a coprocessor instruction wrapped around an
addressing limit (0FFFFH for expand-up segments, zero for expand-down segments) and
spanned inaccessible addresses
(1)
. The failing numerics instruction is not restartable. The
address of the failing numerics instruction and data operand may be lost; an FSTENV does not
return reliable addresses. The segment overrun exception should be handled by executing an
FNINIT instruction (i.e., an FINIT without a preceding WAIT). The exception can be avoided by
never allowing numerics operands to cross the end of a segment.
13
In a protected-mode system, the first word of a numeric operand is not entirely within the limit of
its segment. The return address pushed onto the stack of the exception handler points at the
ESC instruction that caused the exception, including any prefixes. The Math CoProcessor has
not executed this instruction; the instruction pointer and data pointer register refer to a previous,
correctly executed instruction.
16
The previous numerics instruction caused an unmasked exception. The address of the faulty
instruction and the address of its operand are stored in the instruction pointer and data pointer
registers. Only ESC and WAIT instructions can cause this interrupt. The CPU return address
pushed onto the stack of the exception handler points to a WAIT or ESC instruction (including
prefixes). This instruction can be restarted after clearing the exception condition in the Math
CoProcessor. FNINIT, FNCLEX, FNSTSW, FNSTENV, and FNSAVE cannot cause this interrupt.
NOTE:
1.
An operand may wrap around an addressing limit when the segment limit is near an addressing limit and the operand is
near the largest valid address in the segment. Because of the wrap-around, the beginning and ending addresses of such an
operand will be at opposite ends of the segment. There are two ways that such an operand may also span inaccessible
addresses: 1) if the segment limit is not equal to the addressing limit (e.g. addressing limit is FFFFH and segment limit is
FFFDH) the operand will span addresses that are not within the segment (e.g. an 8-byte operand that starts at valid offset
FFFCH will span addresses FFFC–FFFFH and 0000-0003H; however addresses FFFEH and FFFFH are not valid, because
they exceed the limit); 2) if the operand begins and ends in present and accessible segments but intermediate bytes of the
operand fall in a not-present page or in a segment or page to which the procedure does not have access rights.
Table 3-8. Intel387
TM
SX Math CoProcessor Exceptions
Exception
Cause
Default Action
(if exception is masked)
Invalid
Operation
Operation on a signalling NaN, unsupported format,
indeterminate for (0-
%
, 0/0, (
a
%
)
a
(
b
%
), etc.), or stack
overflow/underflow (SF is also set).
Result is a quiet NaN,
integer indefinite, or
BCD indefinte
Denormalized
Operand
At least one of the operands is denormalized, i.e., it has the
smallest exponent but a nonzero significand.
Normal processing
continues
Zero Divisor
The divisor is zero while the dividend is a noninfinite, nonzero
number.
Result is
%
Overflow
The result is too large in magnitude to fit in the specified format.
Result is largest finite
value or
%
Underflow
The true result is nonzero but too small to be represented in the
specified format, and, if underflow exception is masked,
denormalization causes the loss of accuracy.
Result is denormalized
or zero
Inexact Result
(Precision)
The true result is not exactly representable in the specified
format (e.g. 1/3); the result is rounded according to the rounding
mode.
Normal processing
continues
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