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Intel387
TM
SX MATH COPROCESSOR
3.2.2 CONTROL WORD (CW) REGISTER
The Math CoProcessor provides the programmer
with several processing options that are selected by
loading a control word from memory into the control
register. Figure 3-3 show the format and encoding of
fields in the control word.
The low-order byte of the control word register is
used to configure the exception masking. Bits 5–0
of the control word contain individual masks for each
of the six exceptions that the Math CoProcessor rec-
ognizes. See Section 3.5, Exception Handling, for
further explanation on the exception control and def-
inition.
The high-order byte of the control word is used to
configure the Math CoProcessor operating mode, in-
cluding precision, rounding and infinity control.
#
The rounding control (RC) field (bits 11–10) pro-
vide for directed rounding and true chop, as well
as the unbiased round to nearest even mode
specified in the IEEE standard. Rounding control
affects only those instructions that perform
rounding at the end of the operation (and thus
can generate a precision exception); namely,
FST, FSTP, FIST, all arithmetic instructions (ex-
cept FPREM, FPREM1, FXTRACT, FABS, and
FCHS) and all transcendental instructions.
#
The precision control (PC) field (bits 9–8) can be
used to set the Math CoProcessor internal oper-
ating precision of the significand at less than the
default of 64 bits (extended precision). This can
be useful in providing compatibility with early gen-
eration arithmetic processors of smaller preci-
sion. PC affects only the instructions FADD,
FSUB(R), FMUL, FDIV(R), and FSQRT. For all
other instructions, either the precision is deter-
mined by the opcode or extended precision is
used.
#
The ‘‘infinity control bit’’ (bit 12) is not meaningful
to the Intel387 SX Math CoProcessor and pro-
grams must ignore its value. To maintain compat-
ibility with the 8087 and 80287 (non-387 core),
this bit can be programmed, however, regardless
of its value the Intel387 SX Math CoProcessor
always treats infinity in the affine sense (
b
%
k
a
%
). This bit is initialized to zero both after a
hardware reset and after FINIT instruction.
All other bits are reserved and should not be pro-
grammed, to assure compatibility with future proces-
sors.
240225–5
Precision Control
00D24 bits (single precision)
01D(reserved)
10D53 bits (double precision)
11D64 bits (extended precision)
Rounding Control
00DRound to nearest or even
01DRound down (toward
b
%
)
10DRound up (toward
a
%
)
11DChop (truncate toward zero)
Figure 3-3. Control Word
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