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參數(shù)資料
| 型號： | Intel387 sx |
| 廠商： | Intel Corp. |
| 英文描述： | SX Math Coprocessor(32位數(shù)學協(xié)處理器) |
| 中文描述： | 山西數(shù)學協(xié)處理器（32位數(shù)學協(xié)處理器） |
| 文件頁數(shù)： | 41/47頁 |
| 文件大小： | 443K |
| 代理商： | INTEL387 SX |
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Intel387
TM
SX MATH COPROCESSOR
8.0
INTEL387 SX MATH
COPROCESSOR INSTRUCTION
SET
Instructions for the Intel387 SX Math CoProcessor
assume one of the five forms shown in Table 8-1. In
all cases, instructions are at least two bytes long and
begin with the bit pattern 11011B, which identifies
the ESCAPE class of instruction. Instructions that
refer to memory operands specify addresses using
the CPU’s addressing modes.
MOD (Mode field) and R/M (Register/Memory spec-
ifier) have the same interpretation as the corre-
sponding fields of CPU instructions (refer to Pro-
grammer’s Reference Manual for the CPU). SIB
(Scale Index Base) byte and DISP (displacement)
are optionally present in instructions that have MOD
and R/M fields. Their presence depends on the val-
ues of MOD and R/M, as for instructions of the CPU.
The instruction summaries that follow in Table 8-2
assume that the instruction has been prefetched,
decoded, and is ready for execution; that bus cycles
do not require wait states; that there are no local bus
HOLD requests delaying processor access to the
bus; and that no exceptions are detected during in-
struction execution. If the instruction has MOD and
R/M fields that call for both base and index regis-
ters, add one clock.
Table 8-1. Instruction Formats
Instruction
Optional
Fields
First Byte
Second Byte
1
11011
OPA
1
MOD
1
OPB
R/M
SIB
DISP
2
11011
MF
OPA
MOD
OPB
*
R/M
SIB
DISP
3
11011
d
P
OPA
1
1
OPB
*
ST(i)
4
11011
0
0
1
1
1
1
OP
5
11011
0
1
1
1
1
1
OP
15–11
10
9
8
7
6
5
4 3 2 1 0
OP
e
Instruction opcode, possibly split into two fields OPA and OPB
MF
e
Memory Format
00 - 32-bit real
01 - 32-bit integer
10 - 64-bit real
11 - 16-bit integer
d
e
Destination
0 - Destination is ST(0)
1 - Destination is ST(i)
R XOR d
e
0 - Destination (op) Source
R XOR d
e
1 - Source (op) Destination
*
In FSUB and FDIV, the low-order bit of OPB is the R (reversed) bit
P
e
POP
0 - Do not pop stack
1 - Pop stack after operation
ESC
e
11011
ST(i)
e
Register stack element i
000
e
Stack top
001
e
Second stack element
#
#
#
111
e
Eighth stack element
41
41
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相關代理商/技術參數(shù) |
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