參數(shù)資料
型號(hào)： Intel387 sx
廠商： Intel Corp.
英文描述： SX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器)
中文描述： 山西數(shù)學(xué)協(xié)處理器（32位數(shù)學(xué)協(xié)處理器）
文件頁(yè)數(shù)： 24/47頁(yè)
文件大小： 443K
代理商： INTEL387 SX
Intel387
TM
SX MATH COPROCESSOR
4.1.11 BUS READY INPUT (READY
Y
)
This input indicates to the Math CoProcessor when
a CPU bus cycle is to be terminated. It is used by the
bus control logic to trace bus activities. Bus cycles
can be extended indefinitely until terminated by
READY
Y
. This input should be connected to the
same signal that drives the CPU’s READY
Y
input.
Setup and hold times are referenced to CPUCLK2.
4.1.12 READY OUTPUT (READYO
Y
)
This pin is activated at such a time that write cycles
are terminated after two clocks (except FLDENV
and FRSTOR) and read cycles after three clocks. In
configurations where no extra wait states are re-
quired, this pin must directly or indirectly drive the
READY
Y
input of the CPU. Refer to the section enti-
tled ‘‘BUS OPERATION’’ for details. This pin is acti-
vated only during bus cycles that select the Math
CoProcessor. This signal is referenced to CPUCLK2.
(FLDENV and FRSTOR require data transfers larger
than the FIFO. Therefore, PEREQ is activated for
the duration of transferring 2 words of 32 bits and
then deactivated until the FIFO is ready to accept
two additional words. The length of the write cycles
of the last operand word in each transfer as well as
the first operand word transfer of the entire instruc-
tion is 3 clocks instead of 2 clocks. This is done to
give the Intel386 CPU enough time to sample
PEREQ and to notice that the Intel387 is
not
ready
for additional transfers.)
4.1.13 STATUS ENABLE (STEN)
This pin serves as a chip select for the Math Co-
Processor. When inactive, this pin forces BUSY
Y
,
PEREQ, ERROR
Y
and READYO
Y
outputs into a
floating state. D15–D0 are normally floating and will
leave the floating state only if STEN is active and
additional conditions are met (read cycle). STEN
also causes the chip to recognize its other chip se-
lect inputs. STEN makes it easier to do on-board
testing (using the overdrive method) of other chips in
systems containing the Math CoProcessor. STEN
should be pulled up with a resistor so that it can be
pulled down when testing. In boards that do not use
on-board testing STEN should be connected to V
CC
.
Setup and hold times are relative to CPUCLK2. Note
that STEN must maintain the same setup and hold
times as NPS1
Y
, NPS2, and CMD0
Y
(i.e., if STEN
changes state during a Math CoProcessor bus cycle,
it must change state during the same CLK period as
the NPS1
Y
, NPS2, and CMD0
Y
signals).
4.1.14 MATH COPROCESSOR SELECT 1
(NPS1
Y
)
When active (along with STEN and NPS2) in the first
period of a CPU bus cycle, this signal indicates that
the purpose of the bus cycle is to communicate with
the Math CoProcessor. This pin should be connect-
ed directly to the M/IO
Y
pin of the CPU, so that the
Math CoProcessor is selected only when the CPU
performs I/O cycles. Setup and hold times are refer-
enced to the rising edge of CPUCLK2.
4.1.15 MATH COPROCESSOR SELECT 2
(NPS2)
When active (along with STEN and NPS1
Y
) in the
first period of a CPU bus cycle, this signal indicates
that the purpose of the bus cycle is to communicate
with the Math CoProcessor. This pin should be con-
nected directly to the A23 pin of the CPU, so that the
Math CoProcessor is selected only when the CPU
issues one of the I/O addresses reserved for the
Math CoProcessor (8000F8h, 8000FCh, or 8000FEh
which is treated as 8000FCh by the Math CoProces-
sor). Setup and hold times are referenced to the ris-
ing edge of CPUCLK2.
4.1.16 COMMAND (CMD0
Y
)
During a write cycle, this signal indicates whether an
opcode (CMD0
Y
active low) or data (CMD0
Y
inac-
tive high) is being sent to the Math CoProcessor.
During a read cycle, it indicates whether the control
or status register (CMD0
Y
active) or a data register
(CMD0
Y
) is being read. CMD0
Y
should be connect-
ed directly to the A2 output of the CPU. Setup and
hold times are referenced to the rising edge of
CPUCLK2 at the end of PH2.
4.1.17 SYSTEM POWER (V
CC
)
System power provides the
a
5V DC supply input.
All V
CC
pins should be tied together on the circuit
board and local decoupling capacitors should be
used between V
CC
and V
SS
.
4.1.18 SYSTEM GROUND (V
SS
)
System ground provides the 0V connection from
which all inputs and outputs are measured. All V
SS
pins should be tied together on the circuit board and
local decoupling capacitors should be used between
V
CC
and V
SS
.
24
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