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參數(shù)資料
| 型號： | Intel387 sx |
| 廠商： | Intel Corp. |
| 英文描述： | SX Math Coprocessor(32位數(shù)學協(xié)處理器) |
| 中文描述： | 山西數(shù)學協(xié)處理器（32位數(shù)學協(xié)處理器） |
| 文件頁數(shù)： | 29/47頁 |
| 文件大?。?/td> | 443K |
| 代理商： | INTEL387 SX |
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Intel387
TM
SX MATH COPROCESSOR
240225–8
Cycles 1 & 2 represent part of the operand transfer cycle for instructions involving either 4-byte or 8-byte operand loads.
Cycles 3 & 4 represent part of the operand transfer cycle for a store operation.
*
Cycles 1 & 2 could repeat here or T
I
states for various non-operand transfer cycles and overhead.
Figure 5-2. Non-Pipelined Read and Write Cycles
When READY
Y
is asserted, the Math CoProcessor
returns to the idle state. Simultaneously with the
Math CoProcessor entering the idle state, the CPU
may assert ADS
Y
again, signaling the beginning of
yet another cycle.
5.1.2 READ CYCLE
At the rising edge of CLK in the second CLK period
of the cycle (i.e., the first T
RS
state), the Math Co-
Processor starts to drive the D15–D0 outputs and
continues to drive them as long as it stays in T
RS
state.
At least one wait state must be inserted to ensure
that the CPU latches the correct data. Because the
Math CoProcessor starts driving the data bus only at
the rising edge of CLK in the second clock period of
the bus cycle, not enough time is left for the data
signals to propagate and be latched by the CPU be-
fore the next falling edge of CLK. Therefore, the
Math CoProcessor does not drive the READYO
Y
signal until the third CLK period of the cycle. Thus, if
the READYO
Y
output drives the CPU’s READY
Y
input, one wait state is automatically inserted.
Because one wait state is required for Math CoProc-
essor reads, the minimum length of a Math CoProc-
essor read cycle is three CLK periods, as cycle 3 of
Figure 5-2 shows.
When READY
Y
is asserted, the Math CoProcessor
returns to the idle state. Simultaneously with the
Math CoProcessor’s entering the idle state, the CPU
may assert ADS
Y
again, signaling the beginning of
yet another cycle. The transition from T
RS
state to
idle state causes the Math CoProcessor to put the
D15–D0 outputs into the floating state, allowing an-
other device to drive the data bus.
5.2 Pipelined Bus Cycles
Because all the activities of the Math CoProcessor
bus interface occur either during the T
RS
state or
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PDF描述 |
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| INTEL486 GX | Emedded Ultra-Low Power INTEL486 GX Processor(嵌入式超低能量處理器) |
| INTEL486 SX | Emedded Ultra-Low Power INTEL486 SX Processor(嵌入式超低能量處理器) |
| INTEL82801 | 82801AB (ICH0) I/O Controller Hub |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
| INTEL740 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Graphics (GUI) Accelerator |
| INTEL82801 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:82801AB (ICH0) I/O Controller Hub |
| INTEL82802AB | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Firmware Hub (FWH) |
| INTELLIGENT CHARGER + 4AA | 制造商:Energizer 功能描述:Bulk |
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