參數(shù)資料
型號(hào)： Intel387 sx
廠商： Intel Corp.
英文描述： SX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器)
中文描述： 山西數(shù)學(xué)協(xié)處理器（32位數(shù)學(xué)協(xié)處理器）
文件頁(yè)數(shù)： 28/47頁(yè)
文件大?。?/td> 443K
代理商： INTEL387 SX
Intel387
TM
SX MATH COPROCESSOR
During this first CLK period, the Math CoProcessor
also examines the W/R
Y
input signal to determine
whether the cycle is a read or a write cycle and ex-
amines the CMD0
Y
input to determine whether an
opcode, operand, or control/status register transfer
is to occur.
The Intel387 SX Math CoProcessor supports both
pipelined (i.e., overlapped) and non-pipelined bus
cycles. A non-pipelined cycle is one for which the
CPU asserts ADS
Y
when no other bus cycle is in
progress. A pipelined bus cycle is one for which the
CPU asserts ADS
Y
and provides valid next address
and control signals before the prior Math CoProces-
sor cycle terminates. The CPU may do this as early
as the second CLK period after asserting ADS
Y
for
the prior cycle. Pipelining increases the availability of
the bus by at least one CLK period. The Intel387 SX
Math CoProcessor supports pipelined bus cycles in
order to optimize address pipelining by the CPU for
memory cycles.
Bus operation is described in terms of an abstract
state machine. Figure 5-1 illustrates the states and
state transitions for Math CoProcessor bus cycles:
#
T
I
is the idle state. This is the state of the bus
logic after RESET, the state to which bus logic
returns after every non-pipelined bus cycle, and
the state to which bus logic returns after a series
of pipelined cycles.
#
T
RS
is the READY
Y
sensitive state. Different
types of bus cycles may require a minimum of
one or two successive T
RS
states. The bus logic
remains in T
RS
state until READY
Y
is sensed, at
which point the bus cycle terminates. Any number
of wait states may be implemented by delaying
READY
Y
, thereby causing additional successive
T
RS
states.
#
T
P
is the first state for every pipelined bus cycle.
This state is not used by non-pipelined cycles.
Note that the bus logic tracks bus state regardless
of the values on the chip/port select pins. The
240225–7
Figure 5-1. Bus State Diagram
READYO
Y
output of the Math CoProcessor indi-
cates when a Math CoProcessor bus cycle may be
terminated if no extra wait states are required. For all
write cycles (except those for the instructions
FLDENV and FRSTOR), READYO
Y
is always as-
serted during the first T
RS
state, regardless of the
number of wait states. For all read cycles (and write
cycles for FLDENV and FRSTOR), READY
Y
is al-
ways asserted in the second T
RS
state, regardless
of the number of wait states. These rules apply to
both pipelined and non-pipelined cycles. Systems
designers may use READYO
Y
in one of the follow-
ing ways:
1. Connect it (directly or through logic that ORs
READY
Y
signals from other devices) to the
READY
Y
inputs of the CPU and Math CoProces-
sor.
2. Use it as one input to a wait-state generator.
The following sections illustrate different types of
Intel387 SX Math CoProcessor bus cycles. Because
different instructions have different amounts of over-
head before, between, and after operand transfer
cycles, it is not possible to represent in a few dia-
grams all of the combinations of successive operand
transfer cycles. The following bus cycle diagrams
show memory cycles between Math CoProcessor
operand transfer cycles. Note however that, during
FRSTOR, some consecutive accesses to the Math
CoProcessor do not have intervening memory ac-
cesses. For the timing relationship between operand
transfer cycles and opcode write or other overhead
activities, see Figure 7-7 ‘‘Other Parameters’’.
5.1 Non-Pipelined Bus Cycles
Figure 5-2 illustrates bus activity for consecutive
non-pipelined bus cycles.
At the second clock of the bus cycle, the Math Co-
Processor enters the T
RS
state. During this state, it
samples the READY
Y
input and stays in this state
as long as READY
Y
is inactive.
5.1.1 WRITE CYCLE
In write cycles, the Math CoProcessor drives the
READYO
Y
signal for one CLK period during the
second CLK period of the cycle (i.e., the first T
RS
state); therefore, the fastest write cycle takes two
CLK periods (see cycle 2 of Figure 5-2). For the in-
structions FLDENV and FRSTOR, however, the
Math CoProcessor forces wait state by delaying the
activation of READYO
Y
to the second T
RS
state
(not shown in Figure 5-2).
The Math CoProcessor samples the D15–D0 inputs
into data latches at the falling edge of CLK as long
as it stays in T
RS
state.
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