參數(shù)資料
型號： Intel387 sx
廠商： Intel Corp.
英文描述： SX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器)
中文描述： 山西數(shù)學(xué)協(xié)處理器（32位數(shù)學(xué)協(xié)處理器）
文件頁數(shù)： 27/47頁
文件大小： 443K
代理商： INTEL387 SX
Intel387
TM
SX MATH COPROCESSOR
4.4.1 INTEL387 SX MATH COPROCESSOR
ADDRESSING
The NPS1
Y
, NPS2, and CMD0 signals allow the
Math CoProcessor to identify which bus cycles are
intended for the Math CoProcessor. The Math Co-
Processor responds to I/O cycles when the I/O ad-
dress is 8000F8h, 8000FCh, and 8000FEh (treated
as 8000FCh). The Math CoProcessor responds to
I/O cycles when bit 23 of the I/O address is set. In
other words, the Math CoProcessor acts as an I/O
device in a reserved I/O address space.
Because A23 is used to select the Intel387 SX Math
CoProcessor for data transfers, it is not possible for
a program running on the CPU to address the Math
CoProcessor with an I/O instruction. Only ESC in-
structions cause the CPU to communicate with the
Math CoProcessor.
4.4.2 CPU/MATH COPROCESSOR
SYNCHRONIZATION
The pins BUSY
Y
, PEREQ, and ERROR
Y
are used
for various aspects of synchronization between the
CPU and the Math CoProcessor.
BUSY
Y
is used to synchronize instruction transfer
from the CPU to the Math CoProcessor. When the
Math CoProcessor recognizes an ESC instruction it
asserts BUSY
Y
. For most ESC instructions, the
CPU waits for the Math CoProcessor to deassert
BUSY
Y
before sending the new opcode.
The Math CoProcessor uses the PEREQ pin of the
CPU to signal that the Math CoProcessor is ready
for data transfer to or from its data FIFO. The Math
CoProcessor does not directly access memory; rath-
er, the CPU provides memory access services for
the Math CoProcessor. (For this reason, memory ac-
cess on behalf of the Math CoProcessor always
obeys the protection rules applicable to the current
CPU mode.) Once the CPU initiates an Math Co-
Processor instruction that has operands, the CPU
waits for PEREQ signals that indicate when the Math
CoProcessor is ready for operand transfer. Once all
operands have been transferred (or if the instruction
has no operands) the CPU continues program exe-
cution while the Math CoProcessor executes the
ESC instruction.
In 8087/8087 systems, WAIT instructions may be
required to achieve synchronization of both com-
mands and operands. In the Intel386 Micropro-
cessor and Intel387 Math CoProcessor systems,
however, WAIT instructions are required only for op-
erand synchronization; namely, after Math CoProc-
essor stores to memory (except FSTSW and
FSTCW) or load from memory. (In 80286/80287
systems, WAIT is required before FLDENV and
FRSTOR.) Used this way, WAIT ensures that the
value has already been written or read by the Math
CoProcessor before the CPU reads or changes the
value.
Once it has started to execute a numerics instruction
and has transferred and operands from the CPU, the
Math CoProcessor can process the instruction in
parallel with and independent of the host CPU.
When the Math CoProcessor detects an exception,
it asserts the ERROR
Y
signal, which causes a CPU
interrupt.
4.4.3 SYNCHRONOUS/ASYNCHRONOUS
MODES
The internal logic of the Math CoProcessor can op-
erate either directly from the CPU clock (synchro-
nous mode) or from a separate clock (asynchronous
mode). The two configurations are distinguished by
the CKM pin. In either case, the bus control logic
(BCL) of the Math CoProcessor is synchronized with
the CPU clock. Use of asynchronous mode allows
the BCL and the FPU section of the Math CoProces-
sor to run at different speeds. In this case, the ratio
of the frequency of NUMCLK2 to the frequency of
CPUCLK2 must lie within the range 10:16 to 14:10.
Use of synchronous mode eliminates one clock gen-
erator from the board design. The internal Power
Management Unit of the Intel387 SX Math CoProc-
essor is disabled in asynchronous mode.
4.4.4 AUTOMATIC BUS CYCLE TERMINATION
In configurations where no extra wait states are re-
quired, READYO
Y
can drive the CPU’s READY
Y
input and the Math CoProcessors READY
Y
input. If
wait states are required, this pin should be connect-
ed to the logic that ORs all READY outputs from
peripheral devices on the CPU bus. READYO
Y
is
asserted by the Math CoProcessor only during I/O
cycles that select the Math CoProcessor. Refer to
Section 5.0 Bus Operation for details.
5.0
BUS OPERATION
With respect to bus interface, the Intel387 SX Math
CoProcessor is fully synchronous with the CPU.
Both operate at the same rate because each gener-
ates its internal CLK signal by dividing CPUCLK2 by
two. Furthermore, both internal CLK signals are in
phase, because they are synchronized by the same
RESETIN signal.
A bus cycle for the Math CoProcessor starts when
the CPU activates ADS
Y
and drives new values on
the address and cycle definition lines (W/R
Y
,
M/IO
Y
, etc.). The Math CoProcessor examines the
address and cycle definition lines in the same CLK
period during which ADS
Y
is activated. This CLK
period is considered the first CLK of the bus cycle.
27
27
相關(guān)PDF資料
PDF描述
INTEL486 GX Emedded Ultra-Low Power INTEL486 GX Processor(嵌入式超低能量處理器)
INTEL486 SX Emedded Ultra-Low Power INTEL486 SX Processor(嵌入式超低能量處理器)
INTEL82801 82801AB (ICH0) I/O Controller Hub
INTEL82802AB Firmware Hub (FWH)
INTELDX2 High-Performance 32-Bit Embedded Processor(高性能32位嵌入式處理器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
INTEL387TMDX 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR
INTEL740 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Graphics (GUI) Accelerator
INTEL82801 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:82801AB (ICH0) I/O Controller Hub
INTEL82802AB 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Firmware Hub (FWH)
INTELLIGENT CHARGER + 4AA 制造商:Energizer 功能描述:Bulk
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*