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參數(shù)資料
| 型號： | IBM25PPC970FX6UB267ET |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 1800 MHz, RISC PROCESSOR, CBGA576 |
| 封裝： | 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-576 |
| 文件頁數(shù)： | 6/78頁 |
| 文件大?。?/td> | 3524K |
| 代理商： | IBM25PPC970FX6UB267ET |
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Datasheet
PowerPC 970FX RISC Microprocessor
General Information
Page 14 of 78
Version 2.5
March 26, 2007
– Two load or store operations
– Two fixed-point register-to-register operations
– Two floating-point operations
– One branch operation
– One condition register operation
– One vector/SIMD multimedia extension permute operation
– One vector/SIMD multimedia extension arithmetic logic unit (ALU) operation
In-order dispatch of up to five operations into a distributed issue queue structure
Register renaming on general purpose registers (GPRs), floating-point registers (FPRs), Vector Reg-
ister Files (VRFs), condition register (CR) fields, Integer Exception Register (XER), Floating-Point
Status and Control Register (FPSCR), Vector Status and Control Register (VSCR), Vector Register
Save (VRSAVE), and Link and Count
Large number of instructions in flight (theoretical maximum of 215 instructions)
– Up to 16 instructions in the instruction fetch unit (fetch buffer and overflow buffer)
– Up to 32 instructions in the instruction fetch buffer in the instruction decode unit
– Up to 35 instructions in three decode pipe stages and four dispatch buffers
– Up to 100 instructions in the inner-core (after dispatch)
– Up to 32 stores queued in the store queue (STQ) (available for forwarding)
Fast, selective flush of incorrect speculative instructions and results
Specific focus on storage latency management
Out-of-order and speculative issue of load operations
Support for up to eight outstanding L1 cache line misses
Hardware-initiated instruction prefetching from the level 2 (L2) cache
Software-initiated data stream prefetching
– Support for up to eight active streams
Critical word forwarding; critical sector first
New branch processing; prediction hints added to branch instructions
Power management
Static power management
– Software-initiated doze and nap
Dynamic power management
– Parts of the design stop their (hardware-initiated) clocks when not in use
Power tuning engine
– Software-initiated slow down of the processor; selectable to half of the nominal operating fre-
quency
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM25PPC970FX6UB429RT | 制造商:IBM Microelectronics 功能描述:MPU 970FX RISC 64BIT 90NM 1.5V 576CBGA - Trays 制造商:IBM 功能描述:IBM IBM25PPC970FX6UB429RT Co-Processors |
| IBM25PPC970GX7TR01-ET | 制造商:IBM 功能描述:ANTARES GX DD1.0X 1.2GHZ POWER OPTIMIZED - Trays |
| IBM25PPC970GX7TR05-ET | 制造商:IBM 功能描述:ANTARES GX DD1.0X 1.4GHZ POWER OPTIMIZED - Trays |
| IBM25PPC970GX7TR20-ET | 制造商:IBM Microelectronics 功能描述:ANTARES GX DD1.0X 1.6GHZ POWER OPTIMIZED - Trays |
| IBM25PPC970GX7TR23-ET | 制造商:IBM 功能描述:ANTARES GX DD1.0X 1.6GHZ PERFORMANCE OPTIMIZED - Trays |
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