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參數(shù)資料
| 型號： | IBM25PPC970FX6UB267ET |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 1800 MHz, RISC PROCESSOR, CBGA576 |
| 封裝： | 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-576 |
| 文件頁數(shù)： | 54/78頁 |
| 文件大?。?/td> | 3524K |
| 代理商： | IBM25PPC970FX6UB267ET |
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Datasheet
PowerPC 970FX RISC Microprocessor
Dimensions and Physical Signal Assignments
Page 58 of 78
Version 2.5
March 26, 2007
RAMSTOP_ENABLE
AB6
High
Input
RI_B
AA5
Low
Input
SPARE
AA13
—
Input
SPARE2
W4
—
SPARE_GND
N1
—
SRESET_B
AB4
Low
Input
—
SRIN(0:1)
L24, L21
—
PI Input
—
SRIN_B(0:1)
K24, L22
—
PI Input
—
SROUT(0:1)
L3, G1
—
PI Output
—
SROUT_B(0:1)
L2, F1
—
PI Output
—
SYNC_ENABLE
AB24
High
Input
SYSCLK
R22
—
Input
—
SYSCLK_B
T22
—
Input
—
TBEN
AD17
High
Input
—
TCK
AD21
—
Input
TDI
AB21
—
Input
TDO
AD13
—
Output
—
THERM_INT_B
V22
Low
Input
—
TMS
AD22
—
Input
TRIGGERIN
N21
High
Input
—
TRIGGEROUT
N19
High
Output
—
TRST_B
W20
Low
Input
Table 4-2. Pinout Listing for the CBGA Package (Page 4 of 5)
Signal Name
Pin Number
Active
I/O
PI/PO5
Notes
Notes:
1. These are test signals for factory use only and must be pulled up to OVDD for normal system operation.
2. These pins are reserved for potential future use.
3. TCK must be tied high or low for normal system operation. If used, TDI, TMS, and TRST_B must be pulled up to OVDD .
4. These are test signals for factory use only and must be pulled down with a 10 k
Ω resistor to GND for normal system operation.
5. I = Input, O = Output, PI = Processor Interface Input, PO = Processor Interface Output. For additional information, see the Pow-
erPC 970FX RISC Microprocessor Users Manual.
6. These pins can be used to measure on-chip voltage drop and noise. They should be connected to a backside probe point immedi-
ately behind the module. They should not be connected to GND and VDD planes.
7. PSRO_ENABLE, Z_OUT, Z_SENSE, SPARE_GND, and SPARE2 must be tied to GND for correct operation.
8. CKTERM_DIS high disables SYSCLK termination.
9. If GPULDBG = ‘1’ during HRESET transition from low to high: Run power-on reset (POR) in debug mode and stop after each POR
instruction.
If GPULDBG = ‘0’ during HRESET transition from low to high: Run POR once in automatic mode without stopping after each POR
instruction.
Toggling GPULDBG from ‘1’ to ‘0’ later will finish POR debug mode and continue without stopping after each instruction.
10. The PLL_MULT and PLL_RANGE bits can be overwritten by Joint Test Action Group (JTAG) commands, and the BUS_CFG bits
can be changed by scan communication (SCOM) commands during the POR sequence. See the PowerPC 970FX Power On
Reset Application Note for more details.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM25PPC970FX6UB429RT | 制造商:IBM Microelectronics 功能描述:MPU 970FX RISC 64BIT 90NM 1.5V 576CBGA - Trays 制造商:IBM 功能描述:IBM IBM25PPC970FX6UB429RT Co-Processors |
| IBM25PPC970GX7TR01-ET | 制造商:IBM 功能描述:ANTARES GX DD1.0X 1.2GHZ POWER OPTIMIZED - Trays |
| IBM25PPC970GX7TR05-ET | 制造商:IBM 功能描述:ANTARES GX DD1.0X 1.4GHZ POWER OPTIMIZED - Trays |
| IBM25PPC970GX7TR20-ET | 制造商:IBM Microelectronics 功能描述:ANTARES GX DD1.0X 1.6GHZ POWER OPTIMIZED - Trays |
| IBM25PPC970GX7TR23-ET | 制造商:IBM 功能描述:ANTARES GX DD1.0X 1.6GHZ PERFORMANCE OPTIMIZED - Trays |
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