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| 型號： | IBM25PPC970FX6UB267ET |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 1800 MHz, RISC PROCESSOR, CBGA576 |
| 封裝： | 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-576 |
| 文件頁數(shù)： | 26/78頁 |
| 文件大小： | 3524K |
| 代理商： | IBM25PPC970FX6UB267ET |
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Datasheet
PowerPC 970FX RISC Microprocessor
Electrical and Thermal Characteristics
Page 32 of 78
Version 2.5
March 26, 2007
3.5.1.4 Receive Side Characteristics
The receive side contains far-end termination circuitry as shown in Figure 3-4 on page 31 for the single-
ended lines. The total skew from the drive side to the module input pins on the receive side is 350 ps
(SDS +SPCB) between any two signals (clocks or data). The differential clock termination scheme is shown
in Figure 3-5 on page 32. All receivers are pseudo-differential with reference to VREF-SSB and with common-
mode rejection of at least 0.5
× VDD. VREF-SSB can be generated internally by the receive-side circuitry or can
be derived from the supply voltage.
For high-performance operation, the PI supports the inclusion and operation of receive-side circuitry for clock
alignment and individual bit-level deskew. An initialization alignment procedure (IAP) is activated at power-on
reset for bit-level deskew and clock alignment. The IAP uses delay elements in the receive-side circuitry to
first equalize the delay of the incoming data signals and then center the clock transition in the timing window.
The timing parameters for the delay elements and flip-flops that register the data signals are summarized
Table 3-12. Processor Interconnect SSB Receiver Specifications
Symbol
Description
Minimum
Typical
Maximum
Units
Notes
VREF-SSB
SSB reference voltage
0.5
× OVDD
mV
(VOHDC + VOLDC)/2
BclkDC
Bus clock duty cycle
48
50
52
%
TR0
Single-ended terminator
83
110
137
Ω
110
±25%
Figure 3-5. Differential Clock Termination Circuitry
Table 3-13. Processor Interconnect SSB Timing Parameters for the Deskew and Clock Alignment
Symbol
Description
Minimum
Typical
Maximum
Units
Notes
TBIT
Bit time
1/(2
× Bclk)
ns
TDED
Delay element time
increment
18
25
35
ps
Thirty-one delay elements for data
TDEC
Delay element time
increment
18
25
35
ps
Sixty-four delay elements for clock
OVDD
Bclk
RC
OVDD
RC
Bclk
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IBM25PPC970FX6UB429RT | 制造商:IBM Microelectronics 功能描述:MPU 970FX RISC 64BIT 90NM 1.5V 576CBGA - Trays 制造商:IBM 功能描述:IBM IBM25PPC970FX6UB429RT Co-Processors |
| IBM25PPC970GX7TR01-ET | 制造商:IBM 功能描述:ANTARES GX DD1.0X 1.2GHZ POWER OPTIMIZED - Trays |
| IBM25PPC970GX7TR05-ET | 制造商:IBM 功能描述:ANTARES GX DD1.0X 1.4GHZ POWER OPTIMIZED - Trays |
| IBM25PPC970GX7TR20-ET | 制造商:IBM Microelectronics 功能描述:ANTARES GX DD1.0X 1.6GHZ POWER OPTIMIZED - Trays |
| IBM25PPC970GX7TR23-ET | 制造商:IBM 功能描述:ANTARES GX DD1.0X 1.6GHZ PERFORMANCE OPTIMIZED - Trays |
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