
Datasheet
PowerPC 970FX RISC Microprocessor
Version 2.5
March 26, 2007
General Information
1. General Information
1.1 Description
The IBM PowerPC 970FX RISC microprocessor is a 64-bit implementation of the IBM PowerPC family of
reduced instruction set computer (RISC) microprocessors that are based on the PowerPC Architecture. This
microprocessor, also called the PowerPC 970FX, includes a vector single-instruction, multiple-data (SIMD)
facility that supports high-bandwidth data processing and algorithmic-intensive computations. This micropro-
cessor is also designed to support multiple system organizations, including desktop and low-end server appli-
cations, and uniprocessor up through 4-way symmetric multiprocessor configurations.
Note: The terms microprocessor and processor are used interchangeably in this document.
The PowerPC 970FX consists of three main components:
PowerPC 970FX core, which includes vector/SIMD multimedia extension execution units
PowerPC 970FX storage subsystem, which includes core interface logic, noncacheable unit, L2 cache
and controls, and the bus interface unit
PowerPC 970FX pervasive functions
This document also provides pertinent physical characteristics of the PowerPC 970FX single-chip modules.
1.2 Features
64-bit implementation of the PowerPC Architecture (version 2.01)
Binary compatibility for all PowerPC application level code (problem state)
Support for the 32-bit operating system bridge facility
Vector/SIMD multimedia extension
Layered implementation strategy for very high frequency operation
Deeply pipelined design
– 16 stages for most fixed-point register-to-register operations
– 18 stages for most load and store operations (assuming L1 data cache hit)
– 21 stages for most floating-point operations
– 19, 22, and 25 stages for fixed-point, complex-fixed, and floating-point operations, respectively in
the vector arithmetic logic unit (VALU)
– 19 stages for vector/SIMD multimedia extension permute operations
Dynamic instruction cracking for some instructions allows for simpler inner core data flow
– Dedicated data flow for cracking one instruction into two internal operations
– Microcoded templates for longer emulation sequences
Speculative superscalar inner core organization
Aggressive branch prediction
– Prediction for up to two branches per cycle
– Support for up to 16 predicted branches in flight
– Prediction support for branch direction and branch addresses
Out-of-order issue of up to 10 operations into 10 execution pipelines
.