參數(shù)資料
型號: IBM25PPC970FX6UB267ET
元件分類: 微控制器/微處理器
英文描述: 64-BIT, 1800 MHz, RISC PROCESSOR, CBGA576
封裝: 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-576
文件頁數(shù): 55/78頁
文件大?。?/td> 3524K
代理商: IBM25PPC970FX6UB267ET
Datasheet
PowerPC 970FX RISC Microprocessor
Version 2.5
March 26, 2007
Dimensions and Physical Signal Assignments
Page 59 of 78
VDD
B3, B13, C20, D5, D7, D13, D17, D19, D21, D23, E4, E6,
E8, E10, E14, E16, E18, E22, F5, F9, F11, F13, F15, F17,
G6, G8, G10, G12, G14, G16, G18, G22, H5, H7, H9,
H11, H13, H15, H17, H19, J2, J4, J6, J12, J16, J20, K7,
K9, K11, K13, K15, K19, K23, L4, L6, L8, L12, L14, L18,
L20, M5, M7, M11, M13, M15, M17, M21, M23, N2, N4,
N6, N8, N10, N12, N14, N16, N18, N20, P1, P3, P5, P7,
P9, P11, P13, P15, P19, P21, P23, R4, R6, R8, R10, R12,
R14, R16, R18, T1, T3, T5, T7, T9, T13, T17, T23, U2,
U4, U6, U8, U10, U12, U14, U16, U18, U20, U22, V1, V3,
V7, V9, V11, V13, V15, V17, V19, W2, W6, W8, W10,
W12, W14, W16, W18, Y3, Y5, Y7, Y9, Y11, Y15, Y19,
Y22, Y23, AA2, AA4, AA16, AA18, AB1, AB3, AB9, AB13,
AB15, AB17, AB23, AC2, AC4, AC6, AC8, AC12, AC14,
AC18, AC20, AC22, AD3, AD5
—VDD
OVDD
A1,A24,B7, B11, B16, B20, C2, C24, D9, E1, F3, F7, F19,
H24, J1, J8, J10, J14, J18, K5, K17, K21, L10, L16, M1,
M9, N24, P17, T11, T15, T21, W24, Y13, Y17, AA6,
AA24, AD1, AD9, AD15, AD19, AD23
—OVDD
Z_OUT
P2
Z_SENSE
R1
Table 4-2. Pinout Listing for the CBGA Package (Page 5 of 5)
Signal Name
Pin Number
Active
I/O
PI/PO5
Notes
Notes:
1. These are test signals for factory use only and must be pulled up to OVDD for normal system operation.
2. These pins are reserved for potential future use.
3. TCK must be tied high or low for normal system operation. If used, TDI, TMS, and TRST_B must be pulled up to OVDD .
4. These are test signals for factory use only and must be pulled down with a 10 k
Ω resistor to GND for normal system operation.
5. I = Input, O = Output, PI = Processor Interface Input, PO = Processor Interface Output. For additional information, see the Pow-
erPC 970FX RISC Microprocessor Users Manual.
6. These pins can be used to measure on-chip voltage drop and noise. They should be connected to a backside probe point immedi-
ately behind the module. They should not be connected to GND and VDD planes.
7. PSRO_ENABLE, Z_OUT, Z_SENSE, SPARE_GND, and SPARE2 must be tied to GND for correct operation.
8. CKTERM_DIS high disables SYSCLK termination.
9. If GPULDBG = ‘1’ during HRESET transition from low to high: Run power-on reset (POR) in debug mode and stop after each POR
instruction.
If GPULDBG = ‘0’ during HRESET transition from low to high: Run POR once in automatic mode without stopping after each POR
instruction.
Toggling GPULDBG from ‘1’ to ‘0’ later will finish POR debug mode and continue without stopping after each instruction.
10. The PLL_MULT and PLL_RANGE bits can be overwritten by Joint Test Action Group (JTAG) commands, and the BUS_CFG bits
can be changed by scan communication (SCOM) commands during the POR sequence. See the PowerPC 970FX Power On
Reset Application Note for more details.
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