參數(shù)資料
型號(hào)： IBM25PPC970FX6UB267ET
元件分類： 微控制器/微處理器
英文描述： 64-BIT, 1800 MHz, RISC PROCESSOR, CBGA576
封裝： 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-576
文件頁數(shù)： 16/78頁
文件大小： 3524K
代理商： IBM25PPC970FX6UB267ET
Datasheet
PowerPC 970FX RISC Microprocessor
Version 2.5
March 26, 2007
Electrical and Thermal Characteristics
Page 23 of 78
3.1.4 dc Electrical Specifications
Table 3-4. dc Electrical Specifications
Characteristic
Symbol
Voltage
Unit
Notes
Minimum
Maximum
SYSCLK, SYSCLK input high voltage
—
0.7
× OVDD
OVDD + 0.3
V
SYSCLK, SYSCLK input low voltage
—
-0.3
0.3
× OVDD
Processor interface (PI) input high voltage
VIH
(0.5
× OVDD) + 0.2
—
V
PI input low voltage
VIL
—
(0.5
× OVDD) - 0.2
V
NonPI input high voltage
VIH
0.7
× OVDD
—V
NonPI input low voltage
VIL
—0.3
× OVDD
PI output high voltage
VOH
0.78
× OVDD
—V
PI output low voltage
VOL
—
0.22
× OVDD
NonPI output high voltage, IOH = -2 mA
VOH
OVDD - 0.2
—
V
—
NonPI output low voltage, IOL = 2 mA
VOL
—0.2
V
—
Open drain (OD) output low, IOL = 2 mA (CHKSTOP, I2CGO)
VOL
—0.2
V
OD output low, IOL = 5 mA (I2C)
VOL
—0.2
V
Input leakage current, VIN = OVDD, VIN = 0 V
IIN
—60
μA—
Hi-Z (off state) leakage current, VOUT = OVDD, VOUT = 0 V
ITSO
—60
μA—
Input capacitance, VIN = 0 V, frequency = 1 MHz
CIN
—5.0
pF
Notes: See Table 3-2 on page 21 for recommended operating conditions.
1. SYSCLK differential receiver requires high-speed transceiver logic (HSTL) differential signaling level. See the Joint Electron Device
Engineering Council (JEDEC) HSTL standard.
2. See the electrical interface section of the PowerPC 970FX RISC Microprocessor Users Manual. The minimum input must meet the
signal eye opening requirements of the link.
3. The Joint Test Action Group (JTAG) signals TDI, TMS, and TRST do not have internal pullups; therefore, pullups must be added to
the system board. Pullups should be added and adjusted according to the system implementation. These input and outputs meet
the dc specification in the JEDEC standard JESD8-11 for 1.5 V normal power supply range.
4. A 100
Ω split terminator is the test load. Note that a 40 Ω signal driver has an up level of 0.78 × OVDD for VOH and 0.22 × OVDD at
VOL.
5. There are two open drain signals on this type of signal driver: CHKSTOP and I2CGO. The pullup for these nets depend on the Trise
time requirement, net load, and topology. The following examples are two bounding suggestions based on a point-to-point 50
Ω net
with two lengths (5 cm and 61 cm). A 33
Ω series source terminator was added in both runs. A net of 61 cm is recommended.
Examples:
500
Ω pullup dc low level 0.18 V at the receiver
Trise 0.2 V - 0.8 V = 55 ns at 61 cm
Trise 0.2 V - 0.8 V = 10 ns at 5 cm
1 k
Ω pullup dc low level 0.13 V at the receiver
Trise 0.2 V - 0.8 V = 115 ns at 61 cm
Trise 0.2 V - 0.8 V = 20 ns at 5 cm
6. Capacitance values are guaranteed by design and characterization, and are not tested.
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