Debug and Test Interface
14-12
GMS30C7201 Data Sheet
Table 14-3: Provisional Boundary scan AC parameters (units in ns)
The AC parameters are based on simulation results using 0.0pf circuit signal loads.
Delays should be calculated using manufacturers output derating values for the actual
circuit capacitance loading.
The correspondence between boundary-scan cells and system pins, system direction
controls and system output enables is shown below. The cells are listed in the order in
which they are connected in the boundary-scan register, starting with the cell closest
to TDI. All outputs are three-state outputs. All boundary-scan register cells at input pins
can apply tests to the on-chip system logic.
EXTEST/CLAMP guard values specified in the table below should be clocked into the
boundary-scan register (using the SAMPLE/PRELOAD instruction) before the
EXTEST, CLAMP or CLAMPZ instructions are selected to ensure that known data is
applied to the system logic during the test. The INTEST guard values shown in the table
below should be clocked into the boundary-scan register (using the SAMPLE/
PRELOAD instruction) before the INTEST instruction is selected to ensure that all
outputs are disabled. An asterisk in the guard value column indicates that any value can
be submitted (as test requires), but ones and zeros should always be placed as shown.
Symbol
Parameter
Min
Max
Tbscl
TCK low period
50
-
Tbsch
TCK high period
50
-
Tbsis
TMS, TDI setup to TCKr
0
-
Tbsih
TMS, TDI hold from TCKr
2
-
Tbsoh
TDO output hold from TCKf
3
-
Tbsod
TDO output delay from TCKf
-
20
Tbsss
Test mode Data in setup to TCKr
2
-
Tbssh
Test mode Data in hold from TCKf
5
-
Tbsdh
Test mode Data out hold from TCKf
3
-
Tbsdd
Test mode Data out delay from TCKf
-
20
Tbsoe
TDO output enable delay from TCKf
2
15
Tbsoz
Test mode Data enable delay from TCKf
2
15
Tbsde
TDO output disable delay from TCKf
2
15
Tbsdz
Test mode Data disable delay from TCKf
2
15
Tbsr
nTRST minimum pulse width
25
-
Tbsrs
TMS setup to nTRSTr
20
-
Tbsrh
TMS hold from nTRSTr
20
-