Fast AMBA Peripherals
12-33
GMS30C7201 Data Sheet
as
“
bit stuffing
”
and is transparent to the user. The information field within a MIr frame
is placed between the start and stop flags, consisting of an 8-bit address, an optional
8-bit control field, a data field containing any multiple of 8-bits and a 16-bit cyclical
redundancy check (CRC-CCITT). Note that each byte within the address, control and
data fields is transmitted and received LSB first, ending with the byte
’
s MSB. However,
the CRC is transmitted and received MSB first.The MIr frame format is outlined below
in
Figure 12-8: MIr frame format
.
Figure 12-8: MIr frame format
Address Field
The 8-bit address field is used by a transmitter to target a select group of receivers
when multiple stations are connected using the infrared link. The address allows up to
255 stations to be uniquely addressed (00000000 to 11111110). The global address
(11111111) is used to broadcast messages to all stations. The serial port contains an
8-bit register that is used to program a unique address for broadcast recognition as well
as a control bit to enable/disable the address match function. Note that the address of
received frames is stored in the receive buffer along with normal data, and that it is
transmitted and received starting with its LSB and ending with its MSB.
Control Field
The MIr control field is typically 8-bits, but can be any length. The serial port does not
provide any hardware decode support for the control byte, but instead treats all bytes
between the address and the CRC as data. Thus any control bits appear as data to the
programmer. Note that the control field is transmitted and received starting with its LSB
and ending with its MSB.
Data Field
The data field can be any length that is a multiple of 8 bits, including zero. The user
determines the data field length according to the application requirements and
transmission characteristics of the target system. Usually a length is selected which
maximizes the amount of data that can be transmitted per frame, while allowing the
CRC checker to be able to consistently detect all errors during transmission. All data
fields must be a multiple of 8 bits. If a data field that is not a multiple of 8 bits is received,
an abort is signalled and the end of frame tag is set within the receive buffer. Also note
that each byte within the data field is transmitted and received starting with its LSB and
ending with its MSB.
CRC Field
MIr uses the established CCITT cyclical redundancy check (CRC) to detect bit errors
that occur during transmission. A 16-bit CRC-CCITT is computed using the address,
control and data fields, and is included in each frame. A separate CRC generator is
implemented in both the transmit and receive logic. The transmitter calculates a CRC
8 bits
8 bits
8 bits
8 bits
(optional)
Any
Multiple of
8 bits
16 bits
8 bits
Start Flag
0111 1110
Start Flag
0111 1110
Address
Control
Data
CRC-
CCITT
Stop Flag
0111 1110