Fast AMBA Peripherals
12-37
GMS30C7201 Data Sheet
buffer, a new data frame is initiated by transmitting an SIP and a start flag followed by
the transmission of data from the buffer. When the TUR bit is set, an interrupt request
is made. Note that underruns are not generated when the MIr transmitter is first
enabled and is in the idle state (continuously transmits flags).
Receiver Abort Status (RAB)(read/write)
The receiver abort status bit (RAB) is set for two different cases:
when an abort is detected during receipt of an incoming frame
if the stop flag is not received on a byte boundary.
An abort is signalled when seven or more consecutive ones are detected in the
incoming data stream. It is also generated when the end flag is received and it is not
on a byte boundary, which indicates that the address, control and data fields did not add
up to an even multiple of 8-bits. When an abort is detected, the current data byte within
the serial shifter is discarded, the least recent byte (the oldest of the two bytes) of data
in the temporary buffer is moved to the receive buffer (the other byte is discarded), and
the EOF tag is set in the buffer entry that corresponds to the last piece of data that was
received before the frame was aborted. The receiver then enters hunt mode, searching
for a flag. When the RAB bit is set, an interrupt request is made.
Transmit buffer Service Request Flag (TFS)(read-only)
The transmit buffer service request flag (TFS) is a read-only bit that is set when the
transmit buffer is not full and requires service to prevent an underrun. The state of TFS
is also sent to the DMA controller, and may be used to signal a DMA service request.
After the DMA or CPU fills the buffer, the TFS flag (and the service request) is
automatically cleared.
Receive buffer Service Request Flag (RFS) (read-only)
The receive buffer service request flag (RFS) is a read-only bit that is set when the
receive buffer contains valid data. The state of RFS is also sent to the DMA controller,
and may be used to signal a DMA service request. After the DMA or CPU empties the
buffer, the RFS flag (and the service request) is automatically cleared.
Figure 12-9: Bit locations in Mlr status register 0
shows the bit locations
corresponding to the status and flag bits within MIr status register 0. Note that the reset
state of all writable status bits is unknown and must be cleared (by writing a one to
them) before enabling the MIr. Also note that writes to reserved bits are ignored and
reads return zeros.
Figure 12-9: Bit locations in Mlr status register 0
Address: 0h 8001 1080
MISR0
Read/Write &
Read-Only
Bit
7
6
5
4
3
2
1
0
WST1 WST0 RES RFS
TFS RAB
TUR
EIF
Reset
0
0
0
0
0
0