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| 型號(hào)： | GMS30C7201 |
| 英文描述： | 32-Bit RISC Microprocessor(32位 RISC 微處理器) |
| 中文描述： | 32位RISC微處理器（32位的RISC微處理器） |
| 文件頁(yè)數(shù)： | 191/354頁(yè) |
| 文件大?。?/td> | 1639K |
| 代理商： | GMS30C7201 |
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Fast AMBA Peripherals
12-35
GMS30C7201 Data Sheet
continuously calculated using the incoming data stream. If they do not match, the last
byte that was placed within the receive buffer is also flagged with a CRC error. The CRC
value is not placed in the receive buffer.
The MIr protocol permits back to back frames to be received. When this occurs, three
flags separate back to back frames.
Most commercial IrDA transceivers can generate an abort (7 to 13 ones) when their
transmit buffer underruns. The receive logic contains a counter that increments each
time a one is decoded before entering the serial shifter, and is reset any time a zero is
decoded. When seven or more ones are detected, a receiver abort occurs. Note that
data is moved from the serial shifter to the temporary buffer a byte at a time, and seven
consecutive ones may bridge two bytes. For this reason, after an abort is detected, the
remaining data in the serial shifter is discarded along with the most recent byte of data
placed in the temporary buffer. After this data is discarded, the oldest byte of data in the
temporary buffer is placed in the receive buffer, the EOF tag is set within the top entry
of the buffer (next to the byte transferred from the temporary buffer), the receiver abort
interrupt is signalled, and the receiver logic enters hunt mode until it recognizes the next
flag.
If the user disables the receiver during operation, reception of the current data byte is
stopped immediately, the serial shifter and receive buffer are cleared, and all clocks
used by the receive logic are automatically shut off to conserve power.
Transmit Operation
The user may either
“
prime
”
the transmit buffer by filling it with data or allow service
requests to cause the DMA to fill the buffer once the MIr transmitter is enabled. Once
enabled, the transmit logic issues a service request if its buffer is empty. A Serial
Infrared Interaction Pulse (SIP) is transmitted in order to guarantee non-disruptive co-
existence with slower (up to 115.2Kb/s) systems, for example another GMS30C7201
device attempting to use its SIr. This is followed by continuous transmission of flags
until valid data resides within the buffer. Once a byte of data resides at the bottom of
the transmit buffer, it is transferred to the serial shifter, is encoded and shifted out onto
the transmit pin clocked by the programmed baud rate clock. Note that the flag and
CRC value are automatically transmitted and need not be placed in the transmit buffer.
When the transmit buffer is emptied, an interrupt and/or DMA service request is
signalled. If new data is not supplied soon enough, the buffer is completely emptied and
the transmit logic attempts to take additional data from the empty buffer, one of two
actions can be taken as programmed by the user. An underrun can either signal the
normal completion of a frame or an unexpected termination of a frame in progress.
When normal frame completion is selected and an underrun occurs, the transmit logic
transmits the 16-bit CRC value calculated during the transmission of all data within the
frame (including the address and control bytes), followed by a flag to denote the end of
the frame. The transmitter then transmits an SIP followed by a continuous transmission
of flags until data is once again available within the buffer. Once data is available, the
transmitter begins transmission of the next frame.
When unexpected frame termination is selected and an underrun occurs, the transmit
logic outputs an abort and interrupts the CPU. An abort continues to be transmitted until
data is once again available in the transmit buffer. The MIr then transmits an SIP
followed by a double flag and starts the new frame. The off-chip receiver may choose
to ignore the abort and continue to receive data, or to signal the serial port to retry
transmission of the aborted frame.
If the user disables the transmitter during operation, transmission of the current data
byte is stopped immediately, the serial shifter and transmit buffer are cleared, and all
clocks used by the transmit logic are automatically shut off to conserve power.
相關(guān)PDF資料 |
PDF描述 |
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| GMS90C32(中文) | 8-Bit CMOS Microcontrollers( 高性價(jià)比的51單片機(jī) ，片內(nèi)無(wú)ROM,256字節(jié)RAM,工作電壓5V) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| GMS-32H | 制造商:Carlo Gavazzi 功能描述:Manual Motor Starter |
| GMS-32H 8A | 制造商:Carlo Gavazzi 功能描述:MMS UP TO 32A HIGH BREAK 5-8A |
| GMS-32H 0.16A | 制造商:Carlo Gavazzi 功能描述:MMS UP TO 32A HIGH BREAK 0.1-0.16A |
| GMS-32H 0.25A | 制造商:Carlo Gavazzi 功能描述:MMS UP TO 32A HIGH BREAK 0.16-0.25A |
| GMS-32H 0.4A | 制造商:Carlo Gavazzi 功能描述:MMS UP TO 32A HIGH BREAK 0.25-0.4A |
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