Datasheet
vii
Intel
IXP1250 Network Processor
72
73
74
75
76
77
78
79
80
81
82
83
84
SRAM SlowPort Write .......................................................................................133
SRAM SlowPort RDY_L....................................................................................134
Pipelined SRAM Two Longword Burst Read Followed By SlowPort Write .......135
SDCLK AC Timing Diagram..............................................................................136
SDRAM Bus Signal Timing ...............................................................................137
SDRAM Initialization Sequence ........................................................................140
SDRAM Read Cycle..........................................................................................141
SDRAM Write Cycle..........................................................................................142
SDRAM Read-Modify-Write Cycle ....................................................................143
IXP1250 Part Marking.......................................................................................144
520-HL-PBGA Package - Bottom View.............................................................145
IXP1250 Side View............................................................................................145
IXP1250 A-A Section View................................................................................146
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
64-bit IX Bus Receive Remainder Cycles, No Status Transfer...........................13
64-bit IX Bus Receive Remainder Cycles, with Status Transfer .........................13
32-bit IX Bus Receive Remainder Cycles, No Status Transfer...........................13
32-bit IX Bus Receive Remainder Cycles, with Status Transfer .........................14
SDRAM CRC Types............................................................................................17
SDRAM Configurations.......................................................................................18
SRAM Configurations..........................................................................................20
BootROM x32 Sample Configurations ................................................................21
BootROM x16 Sample Configurations ................................................................21
PCI Configuration Options...................................................................................23
Signal Type Abbreviations...................................................................................27
Processor Support Pins.......................................................................................28
SRAM Interface Pins...........................................................................................29
SDRAM Interface Pins ........................................................................................31
IX Bus Interface Pins...........................................................................................33
General Purpose I/Os..........................................................................................37
Serial Port (UART) Pins ......................................................................................37
PCI Interface Pins ...............................................................................................38
Power Supply Pins..............................................................................................41
IEEE 1149.1 Interface Pins.................................................................................42
Miscellaneous Test Pins......................................................................................42
Pin Usage Summary ...........................................................................................43
Pin Table in Pin Order.........................................................................................44
Pin Table in Alphabetical Order...........................................................................49
64-Bit Bidirectional IX Bus, 1-2 MAC Mode.........................................................55
64-Bit Bidirectional IX Bus, 3+ MAC Mode (Shared IX Bus Operation Only in
This Mode) ..........................................................................................................57
32-Bit Unidirectional IX Bus, 1-2 MAC Mode ......................................................60
32-bit Unidirectional IX Bus, 3+ MAC Mode........................................................62
IX Bus Decode Table Listed by Operating Mode Type.......................................63
Pin State During Reset........................................................................................65
Absolute Maximum Ratings.................................................................................68
Functional Operating Range ...............................................................................69
Typical and Maximum Power..............................................................................69
27
28
29
30
31
32
33