參數(shù)資料
型號： GCIXP1250-200
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 14/148頁
文件大?。?/td> 1601K
代理商： GCIXP1250-200
Intel
IXP1250 Network Processor
14
Datasheet
In both 32-bit and 64-bit modes, all of the associated FBE_L signals (FBE_L[7:4] in 32-bit mode
and FBE_L[7:0] for 64-bit mode) are driven low on a transmit. The last bus transfer, identified by
the assertion of EOP in 64-bit mode or by EOP32 in 32-bit mode, indicates the number of valid
bytes of this last transfer by driving only the valid FBE_L signals.
Similarly for receive cycles, in both 32-bit and 64-bit modes, all associated FBE_L signals must be
driven low by the peripheral or MAC device. The FBE_L signals must identify the number of valid
bytes on the last transfer driven with EOP. The IXP1250 uses this information to update the
RCV_CTL register
’
s Valid Bytes field. Driving fewer than the four or eight FBE_Ls, except for the
last transfer with EOP, may cause undefined behavior.
2.4.1.1
Reset and Idle Bus Considerations
While the IXP1250 is in reset, or when the IX Bus is idle for at least 4 FCLK cycles and no IX Bus
requests are pending, the IXP1250 drives the pins listed below. This is done so that the bus is not
left in a high-Z state for a prolonged period of time. This allows the designer to avoid the use of
keeper resistors on the pins to maintain valid levels.
FDAT[63:0]
FBE_L[7:0]
FPS[2:0]
TXAXIS
RDYBUS[7:0]
RDYCTL_L[3:0]
RDYCTL_L[4]
EOP
SOP
EOP32
SOP32
RXFAIL
In shared IX Bus mode, pullups should be used on PORTCTL_L[3:0], FPS[2:0], and TXAXIS to
maintain valid logic levels during bus exchanges.
In configurations where two IXP1250s are in Shared IX Bus Mode, the IXP1250s must be reset
synchronously, preferably with the same signal driving RESET_IN_L. During reset, the IXP1250s
drive the pins listed above to identical logic states thereby avoiding logic state contention. If the
Table 4. 32-bit IX Bus Receive Remainder Cycles, with Status Transfer
EOP signaled on this
cycle:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Number of bus cycles in
burst:
5
6
7
8
9
10
11
12
13
14
15
16
16
16
16
16
Status
transfer
32-bit status
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
N
o
t
e
1
64-bit status
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Number of Don
’
t Care
cycles:
3
3
3
3
3
3
3
3
3
3
3
3
2
1
0
0
NOTE:
1. Status transfer occurs on one or two subsequent IX Bus cycles.
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