參數(shù)資料
型號： GCIXP1250-232
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 1/148頁
文件大小： 1601K
代理商： GCIXP1250-232
Intel
IXP1250 Network Processor
Datasheet
Product Features
The Intel
IXP1250 Network Processor delivers high-performance processing
power and flexibility to a wide variety of LAN and telecommunications
products. Distinguishing features of the IXP1250 are the performance of ASIC
hardware along with programmability of a microprocessor.
I
Applications
—
Multi-layer LAN Switches
—
Multi-protocol Telecommunications Products
—
Broadband Cable Products
—
Remote Access Devices
—
Intelligent PCI adapters
I
Integrated StrongARM* Core
—
High-performance, low-power, 32-bit
Embedded RISC processor
—
16 Kbyte instruction cache
—
8 Kbyte data cache
—
512 byte mini-cache for data that is used once
and then discarded
—
Write buffer
—
Memory management unit
—
Access to IXP1250 FBI Unit, PCI Unit and
SDRAM Unit via the ARM* AMBA Bus
I
Six Integrated Programmable Microengines
—
Operating frequency of up to 232 MHz
—
Multi-thread support of four threads per
microengine
—
Single-cycle ALU and shift operations
—
Zero context swap overhead
—
Large Register Set: 128 General-Purpose and
128 Transfer Registers
—
2 K x 32-bit Instruction Control Store
—
Access to the IXP1250 FBI Unit, PCI DMA
channels, SRAM, and SDRAM
I
High Bandwidth I/O Bus (IX Bus)
—
64-bit, up to 104 MHz operaton
—
6.6 Gbps peak bandwidth
—
64-bit or dual 32-bit bus options
I
Integrated 32-bit, 66 MHz PCI Interface
—
Supports
PCI Local Bus Specification
Revision 2.2
as a Bus Master
—
264 Mbytes/sec peak burst mode operation
—
I
2
O* support for StrongARM Core
—
Dual DMA channels
I
Industry Standard 64-bit SDRAM Interface
—
Peak bandwidth of up to 928 Mbytes/sec
—
Address up to 256 Mbytes of SDRAM
—
Memory bandwidth improvement through
bank switching
—
Read-modify-write support
—
Byte aligner/merger
—
Cyclic Redundancy Check (CRC)
—
Error Correction Code (ECC)
I
Industry Standard 32-bit SRAM Interface
—
Peak bandwidth of up to 464 Mbytes/sec
—
Address up to 8 Mbytes of SRAM
—
Up to 8 Mbytes FlashROM for booting
StrongARM Core
—
Supports atomic push/pop operations
—
Supports atomic bit set and bit clear
operations
—
Memory bandwidth imporvement by reduced
read/write turnaround bus cycles
I
Other Integrated Features
—
Hardware Hash Unit for generation of 48- or
64-bit adaptive polynomial hash keys
—
Serial UART port
—
Real Time Clock
—
Four general-purpose I/O pins
—
Four 24-bit timers with CPU watchdog
support
—
Limited JTAG Support
—
4 Kbyte Scratchpad Memory
I
520-pin, HL-PBGA package
I
2 V CMOS device
—
3.3 V tolerant I/O
Order Number: 278371-006
December 2001
Notice:
This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
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