參數(shù)資料
型號: GCIXP1250-232
英文描述: Microprocessor
中文描述: 微處理器
文件頁數(shù): 34/148頁
文件大小: 1601K
代理商: GCIXP1250-232
Intel
IXP1250 Network Processor
34
Datasheet
[30]
[29]
[28]
[27]
[26]
[25]
[24]
[23]
[22]
[21]
[20]
[19]
[18]
[17]
[16]
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
AK22
AH21
AJ21
AK21
AG20
AH20
AJ20
AK20
AL20
AG19
AH19
AJ19
AK19
AL19
AG18
AH18
AJ18
AK18
AL18
AG17
AH17
AJ17
AK17
AL15
AK15
AJ15
AH15
AG15
AL14
AK14
AJ14
FBE_L[7:0]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
AH14
AG14
AL13
AK13
AJ13
AH13
AG13
AL12
I2/O5/
TS
8
Bidirectional Byte Enables.
64-bit bidirectional IX Bus mode. Bits [7:0] indicate transmit
and receive valid bytes on FDAT[63:0].
32-bit unidirectional IX Bus mode. Bits [7:4] are used to
indicate valid transmit bytes on FDAT[63:32] and bits [3:0]
are used to indicate valid receive bytes on FDAT[31:0].
In a shared IX Bus system, these pins will be tri-stated when
passing ownership of the IX Bus.
TXASIS
AH12
O4/TS 1
Transmit As Is.
TXASIS states are output according to values programmed
in the TFIFO control field. TXASIS value driven coincident
with SOP/SOP_TX signal.
In a shared IX Bus system, this pin will be tri-stated when
passing ownership of the IX Bus.
RXFAIL
AG12
I1/O1/
TS
1
Receive Packet Failure. As input, asserted by a MAC device
if a packet was received with errors. Mimics the behavior of
EOP to terminate an IX Bus cycle.
As output, driven when no receive cycle in-progress.
In a shared IX Bus system, these pins will be tri-stated when
passing ownership of the IX Bus.
FAST_RX1
AK11
I1
1
Ready Input from Fast Port 0 (i.e., Gigabit port). Pulldown
through 10 KOhms to VSS if not used.
FAST_RX2
AJ11
I1
1
Ready Input from Fast Port 1 (i.e., Gigabit port). Pulldown
through 10 KOhms to VSS if not used.
Table 15. IX Bus Interface Pins (Continued)
IX Bus Signal
Names
Pin
Number
Type
Total
Pin Descriptions
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